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Bug fixes #31

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merged 9 commits into from
Nov 6, 2023
Merged

Bug fixes #31

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e4ae80a
Interrupt logic improvements
Peter-Herrmann Nov 6, 2023
10642f1
One more try with 10 SRAMs
Peter-Herrmann Nov 6, 2023
b720c3b
Revert "One more try with 10 SRAMs" (Back to 8)
Peter-Herrmann Nov 6, 2023
f378abd
Merge branch 'sub5' into bug-fixes
Peter-Herrmann Nov 6, 2023
e6d55c2
Down to 6 SRAMs
Peter-Herrmann Nov 6, 2023
0552563
7 SRAMs
Peter-Herrmann Nov 6, 2023
48786a5
Timer fixes
Peter-Herrmann Nov 6, 2023
d432eab
6 SRAMs
Peter-Herrmann Nov 6, 2023
ff79d5c
7 SRAMs again, fixed placement
Peter-Herrmann Nov 6, 2023
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2 changes: 1 addition & 1 deletion openlane/user_project_wrapper/config.json
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Original file line number Diff line number Diff line change
Expand Up @@ -76,7 +76,7 @@
"ROUTING_CORES": 20,
"KLAYOUT_XOR_THREADS": 20,
"FP_IO_UNMATCHED_ERROR": 0,
"FP_PDN_MACRO_HOOKS": "soc_i.sram.sram0 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram1 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram2 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram3 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram4 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram5 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram6 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram7 vccd1 vssd1 vccd1 vssd1",
"FP_PDN_MACRO_HOOKS": "soc_i.sram.sram0 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram1 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram2 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram3 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram4 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram5 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram6 vccd1 vssd1 vccd1 vssd1",
"CLOCK_PORT": "user_clock2",
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 2920 3520",
Expand Down
7 changes: 3 additions & 4 deletions openlane/user_project_wrapper/macro.cfg
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Expand Up @@ -3,7 +3,6 @@ soc_i.sram.sram1 376.9 1134.5 MY
soc_i.sram.sram2 376.9 1968.97 R180
soc_i.sram.sram3 376.9 2803.46 MY

soc_i.sram.sram4 1860 300 MX
soc_i.sram.sram5 1860 1134.5 R0
soc_i.sram.sram6 1860 1968.97 MX
soc_i.sram.sram7 1860 2803.46 R0
soc_i.sram.sram4 1860 1134.5 R0
soc_i.sram.sram5 1860 1968.97 MX
soc_i.sram.sram6 1860 2803.46 R0
2 changes: 2 additions & 0 deletions verilog/rtl/include/clam-defs.svh
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Expand Up @@ -24,4 +24,6 @@ typedef enum logic {
`define SOC_NUM_INTER 52
// `include "Peripheral_Unit_Defs"

`define CARAVEL_INTR_ADDR 32'hF0000000

`endif // CLAM_DEFS_SVH
52 changes: 26 additions & 26 deletions verilog/rtl/peripherals/Peripheral_Unit/PeriphControlRegFile.sv
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Expand Up @@ -592,8 +592,8 @@ module PeriphControlRegFile #(
end
for (g = 0; g < `TIM_INST_NUM; g++) begin
assign TIM_CTRL_WR[g] = ((((ADDR & ~STARTING_ADDR) >> ADDR_SCALE) == (TIM_ADDR_OFFSET + `NUM_TIM_REGS * g)) && WRITE)?1:0;
assign TIM_THRESH_H_WR[g] = ((((ADDR & ~STARTING_ADDR) >> ADDR_SCALE) == (TIM_ADDR_OFFSET + `NUM_TIM_REGS * g + 1)) && WRITE)?1:0;
assign TIM_THRESH_L_WR[g] = ((((ADDR & ~STARTING_ADDR) >> ADDR_SCALE) == (TIM_ADDR_OFFSET + `NUM_TIM_REGS * g + 2)) && WRITE)?1:0;
assign TIM_THRESH_L_WR[g] = ((((ADDR & ~STARTING_ADDR) >> ADDR_SCALE) == (TIM_ADDR_OFFSET + `NUM_TIM_REGS * g + 1)) && WRITE)?1:0;
assign TIM_THRESH_H_WR[g] = ((((ADDR & ~STARTING_ADDR) >> ADDR_SCALE) == (TIM_ADDR_OFFSET + `NUM_TIM_REGS * g + 2)) && WRITE)?1:0;
end
for (g = 0; g < `UART_INST_NUM; g++) begin
assign UART_CR_WR[g] = ((((ADDR & ~STARTING_ADDR) >> ADDR_SCALE) == (UART_ADDR_OFFSET + `NUM_UART_REGS * g)) && WRITE)?1:0;
Expand Down Expand Up @@ -938,17 +938,17 @@ module PeriphControlRegFile #(
36: PWM_MOD_SETPOINT_4 <= DIN;
37: PWM_EN_4 <= DIN;
39: TIM_CTRL_1 <= DIN;
40: TIM_THRESH_H_1 <= DIN;
41: TIM_THRESH_L_1 <= DIN;
40: TIM_THRESH_L_1 <= DIN;
41: TIM_THRESH_H_1 <= DIN;
45: TIM_CTRL_2 <= DIN;
46: TIM_THRESH_H_2 <= DIN;
47: TIM_THRESH_L_2 <= DIN;
46: TIM_THRESH_L_2 <= DIN;
47: TIM_THRESH_H_2 <= DIN;
51: TIM_CTRL_3 <= DIN;
52: TIM_THRESH_H_3 <= DIN;
53: TIM_THRESH_L_3 <= DIN;
52: TIM_THRESH_L_3 <= DIN;
53: TIM_THRESH_H_3 <= DIN;
57: TIM_CTRL_4 <= DIN;
58: TIM_THRESH_H_4 <= DIN;
59: TIM_THRESH_L_4 <= DIN;
58: TIM_THRESH_L_4 <= DIN;
59: TIM_THRESH_H_4 <= DIN;
63: UART_CR_1 <= DIN;
64: UART_TX_RATE_DIV_1 <= DIN;
65: UART_RX_RATE_DIV_1 <= DIN;
Expand Down Expand Up @@ -1140,28 +1140,28 @@ module PeriphControlRegFile #(
37: DOUT <= PWM_EN_4;
38: DOUT <= PWM_SR_4;
39: DOUT <= TIM_CTRL_1;
40: DOUT <= TIM_THRESH_H_1;
41: DOUT <= TIM_THRESH_L_1;
42: DOUT <= TIM_OUT_H_1;
43: DOUT <= TIM_OUT_L_1;
40: DOUT <= TIM_THRESH_L_1;
41: DOUT <= TIM_THRESH_H_1;
42: DOUT <= TIM_OUT_L_1;
43: DOUT <= TIM_OUT_H_1;
44: DOUT <= {31'b0, TIM_INT_REG[0]};
45: DOUT <= TIM_CTRL_2;
46: DOUT <= TIM_THRESH_H_2;
47: DOUT <= TIM_THRESH_L_2;
48: DOUT <= TIM_OUT_H_2;
49: DOUT <= TIM_OUT_L_2;
46: DOUT <= TIM_THRESH_L_2;
47: DOUT <= TIM_THRESH_H_2;
48: DOUT <= TIM_OUT_L_2;
49: DOUT <= TIM_OUT_H_2;
50: DOUT <= {31'b0, TIM_INT_REG[1]};
51: DOUT <= TIM_CTRL_3;
52: DOUT <= TIM_THRESH_H_3;
53: DOUT <= TIM_THRESH_L_3;
54: DOUT <= TIM_OUT_H_3;
55: DOUT <= TIM_OUT_L_3;
52: DOUT <= TIM_THRESH_L_3;
53: DOUT <= TIM_THRESH_H_3;
54: DOUT <= TIM_OUT_L_3;
55: DOUT <= TIM_OUT_H_3;
56: DOUT <= {31'b0, TIM_INT_REG[2]};
57: DOUT <= TIM_CTRL_4;
58: DOUT <= TIM_THRESH_H_4;
59: DOUT <= TIM_THRESH_L_4;
60: DOUT <= TIM_OUT_H_4;
61: DOUT <= TIM_OUT_L_4;
58: DOUT <= TIM_THRESH_L_4;
59: DOUT <= TIM_THRESH_H_4;
60: DOUT <= TIM_OUT_L_4;
61: DOUT <= TIM_OUT_H_4;
62: DOUT <= {31'b0, TIM_INT_REG[3]};
63: DOUT <= UART_CR_1;
64: DOUT <= UART_TX_RATE_DIV_1;
Expand Down
8 changes: 4 additions & 4 deletions verilog/rtl/peripherals/Peripheral_Unit/Timer.sv
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Expand Up @@ -18,7 +18,8 @@ module Timer (
input [31:0] mtimecmp_in_l,
output logic [31:0] mtime_h, // Top 32 of 64 bit timer
output logic [31:0] mtime_l, // Bottom 32 of 64 bit timer
output logic timer_int
output logic timer_int,
output logic timer_pulse
);
logic [63:0] mtime = 0;
logic [63:0] mtimecmp = -1;
Expand All @@ -36,7 +37,8 @@ module Timer (
begin
mtime_h = mtime[63:32];
mtime_l = mtime[31:0];
timer_int = ( mtime == mtimecmp ) ? 1 : 0;
timer_int = ( mtime >= mtimecmp ) ? 1 : 0;
timer_pulse = ( mtime == mtimecmp ) ? 1 : 0;
end

always_ff @ (posedge CLK)
Expand All @@ -60,8 +62,6 @@ module Timer (
mtimecmp [63:32] <= mtimecmp_in_h;
if (en_r)
mtime <= mtime + 1;
if (mtime == mtimecmp)
mtime <= 0;
end
end

Expand Down
6 changes: 4 additions & 2 deletions verilog/rtl/peripherals/Peripheral_Unit/peripheral_unit.sv
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Expand Up @@ -189,6 +189,7 @@ module peripheral_unit (
logic [31:0] TIM_OUT_H [`TIM_INST_NUM - 1: 0];
logic [31:0] TIM_OUT_L [`TIM_INST_NUM - 1: 0];
logic [`TIM_INST_NUM - 1: 0] TIM_INT;
logic [`TIM_INST_NUM - 1: 0] TIM_PULSE;
logic [`TIM_INST_NUM - 1: 0] TIM_CTRL_WR;
logic [`TIM_INST_NUM - 1: 0] TIM_THRESH_H_WR;
logic [`TIM_INST_NUM - 1: 0] TIM_THRESH_L_WR;
Expand All @@ -207,7 +208,8 @@ module peripheral_unit (
.mtimecmp_in_l(TIM_THRESH_L[tim_gv1]),
.mtime_h(TIM_OUT_H[tim_gv1]),
.mtime_l(TIM_OUT_L[tim_gv1]),
.timer_int(TIM_INT[tim_gv1]));
.timer_int(TIM_INT[tim_gv1]),
.timer_pulse(TIM_PULSE[tim_gv1]));
end
endgenerate

Expand Down Expand Up @@ -740,7 +742,7 @@ module peripheral_unit (
.TIM_THRESH_L_4(TIM_THRESH_L[3]),
.TIM_OUT_H_4(TIM_OUT_H[3]),
.TIM_OUT_L_4(TIM_OUT_L[3]),
.TIM_INT(TIM_INT),
.TIM_INT(TIM_PULSE),
.TIM_CTRL_WR(TIM_CTRL_WR),
.TIM_THRESH_H_WR(TIM_THRESH_H_WR),
.TIM_THRESH_L_WR(TIM_THRESH_L_WR),
Expand Down
2 changes: 2 additions & 0 deletions verilog/rtl/rtl/soc/clam-defs.svh
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Expand Up @@ -24,4 +24,6 @@ typedef enum logic {
`define SOC_NUM_INTER 52
// `include "Peripheral_Unit_Defs"

`define CARAVEL_INTR_ADDR 32'hF0000000

`endif // CLAM_DEFS_SVH
2 changes: 2 additions & 0 deletions verilog/rtl/rtl/soc/modules/clam-defs.svh
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Expand Up @@ -25,4 +25,6 @@ typedef enum logic {
`define SOC_NUM_INTER 52
// `include "Peripheral_Unit_Defs"

`define CARAVEL_INTR_ADDR 32'hF0000000

`endif // CLAM_DEFS_SVH
22 changes: 2 additions & 20 deletions verilog/rtl/rtl/soc/modules/sram_wrap.sv
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Expand Up @@ -12,7 +12,7 @@

module sram_wrap #(
parameter SRAM_BASE_ADDR = 32'h8000_0000,
parameter SRAM_NUM_BLOCKS = 8,
parameter SRAM_NUM_BLOCKS = 7,
parameter SRAM_BLOCK_SIZE = 512,
parameter SRAM_LOG_BLOCK_SIZE = $clog2(SRAM_BLOCK_SIZE),
parameter SRAM_END_ADDR = (SRAM_BASE_ADDR + (SRAM_NUM_BLOCKS * SRAM_BLOCK_SIZE)),
Expand Down Expand Up @@ -208,7 +208,7 @@ module sram_wrap #(
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[5])
);

sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram6 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // 1.8V
Expand All @@ -227,24 +227,6 @@ module sram_wrap #(
.dout1 (sram_i_read_vec[6])
);

sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram7 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // 1.8V
.vssd1(vssd1), // Digital ground
`endif
.clk0 (clk_i),
.csb0 (~cs_data[7]), // Active Low
.web0 (~sram_d_we_i), // Active Low
.wmask0 (sram_d_be_i),
.addr0 (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
.din0 (sram_d_wdata_i),
.dout0 (sram_d_read_vec[7]),
.clk1 (clk_i),
.csb1 (~cs_inst[7]), // Active Low
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[7])
);


`ifdef VERILATOR
logic [31:0] _unused;
Expand Down
6 changes: 3 additions & 3 deletions verilog/rtl/rtl/soc/soc.sv
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Expand Up @@ -742,9 +742,9 @@ module soc (

end

assign caravel_interrupt_o = illegal_access;


always_comb begin: caravel_interrupt_assignment
caravel_interrupt_o = ((dmem_addr == `CARAVEL_INTR_ADDR) & dmem_we) ? {dmem_wdata[1:0],1'b0} : {2'b0, illegal_access};
end
////////////////////////////////
// Unused Signal Terminations //
////////////////////////////////
Expand Down
8 changes: 4 additions & 4 deletions verilog/rtl/user_defines.v
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Expand Up @@ -57,10 +57,10 @@
`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP
`define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
`define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_USER_STD_OUTPUT
`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_USER_STD_OUTPUT
`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_OUTPUT
`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_USER_STD_OUTPUT
`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_USER_STD_OUTPUT
`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL

// Configurations of GPIO 14 to 24 are used on caravel but not caravan.
`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_USER_STD_OUTPUT
Expand Down
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