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@Cal-Poly-RAMP

Cal Poly CARP

The Cal Poly CARP SoC Design Framework

Computer Architecture Research Project (CARP)

Welcome to the home of Cal Poly's CARP, an ongoing group/club dedicated to open source chip design.

Getting Started

Note on Submodules

Many repositories in this organization rely on eachother, and use submodules to handle this. After cloning a repo, be sure to immediately initiate and update submodules:

git submodule init
git submodule update --recursive

Tools

All of these tools work best on Linux.

  • If you are on Windows, install WSL2. Complete the following installations from within WSL. Also see using WSL with VSCode.
  • If you are on Mac, you can install tools natively, with varying support.

OSS Cad Suite

OSS Cad Suite bundles all of the necessary open source tools for digital design, inclduing:

  • Verilator for Linting & Simulation
  • CocoTB for Testing
  • Yosys for Synthesis
  • GTKWave for viewing waveforms

To install, follow the instructions here: https://github.com/YosysHQ/oss-cad-suite-build

In summary,

  1. Download the archive depending on your system here: https://github.com/YosysHQ/oss-cad-suite-build/releases/latest
  2. Extract it to somewhere accessible, such as your home directory ~
  3. Run the following command in EVERY terminal that needs OSS Cad Suite Tools: source <extracted_location>/oss-cad-suite/environment

RISC-V Toolchain

The RISC-V toolchain lets us compile C and Assembly files to get RISC-V machine code, as well as debug that code.

To install on Linux or WSL, follow the instructions here: https://github.com/stnolting/riscv-gcc-prebuilt

Example Installation on Linux:

wget https://github.com/stnolting/riscv-gcc-prebuilt/releases/download/rv32i-131023/riscv32-unknown-elf.gcc-13.2.0.tar.gz
sudo mkdir /opt/riscv
sudo tar -xzf riscv32-unknown-elf.gcc-13.2.0.tar.gz -C /opt/riscv/
echo "PATH=\$PATH:/opt/riscv/bin" >> ~/.bashrc

To install on Mac, follow these instructions: https://github.com/riscv-software-src/homebrew-riscv

Popular repositories Loading

  1. ramp-core ramp-core Public

    RAMP's out of order RV32G processor, implemented with PyMTL3

    Python 2

  2. CARPOpenLane CARPOpenLane Public

    Forked from The-OpenROAD-Project/OpenLane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

    Verilog 1

  3. tapeout-ci-2311 tapeout-ci-2311 Public template

    caravel-user repository for November 6, 2023 tapeout

    Verilog 1 1

  4. cal-poly-ramp.github.io cal-poly-ramp.github.io Public

    Website for the RAMP framework

    HTML

  5. style-guide style-guide Public

    The SystemVerilog style guide for the RAMP framework.

  6. basejump_stl basejump_stl Public

    Forked from bespoke-silicon-group/basejump_stl

    BaseJump STL: A Standard Template Library for SystemVerilog

    SystemVerilog

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