Down to 6 SRAMs

Cal-Poly-RAMP · Nov 6, 2023 · e6d55c2 · e6d55c2
1 parent f378abd
commit e6d55c2
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Showing 3 changed files with 8 additions and 46 deletions.
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
@@ -76,7 +76,7 @@
     "ROUTING_CORES": 20,
 	"KLAYOUT_XOR_THREADS": 20,
 	"FP_IO_UNMATCHED_ERROR": 0,
-    "FP_PDN_MACRO_HOOKS": "soc_i.sram.sram0 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram1 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram2 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram3 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram4 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram5 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram6 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram7 vccd1 vssd1 vccd1 vssd1",
+    "FP_PDN_MACRO_HOOKS": "soc_i.sram.sram0 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram1 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram2 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram3 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram4 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram5 vccd1 vssd1 vccd1 vssd1",
 	"CLOCK_PORT": "user_clock2",
     "FP_SIZING": "absolute",
     "DIE_AREA": "0 0 2920 3520",

diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
@@ -1,9 +1,7 @@
-soc_i.sram.sram0 376.9 300 R180
-soc_i.sram.sram1 376.9 1134.5 MY
-soc_i.sram.sram2 376.9 1968.97 R180
-soc_i.sram.sram3 376.9 2803.46 MY
+soc_i.sram.sram0 376.9 250.38 MY
+soc_i.sram.sram1 376.9 1466.92 R180
+soc_i.sram.sram2 376.9 2683.46 MY
 
-soc_i.sram.sram4 1860 300 MX
-soc_i.sram.sram5 1860 1134.5 R0
-soc_i.sram.sram6 1860 1968.97 MX
-soc_i.sram.sram7 1860 2803.46 R0
+soc_i.sram.sram3 1860 250.38 R0
+soc_i.sram.sram4 1860 1466.92 MX
+soc_i.sram.sram5 1860 2683.46 R0
diff --git a/verilog/rtl/rtl/soc/modules/sram_wrap.sv b/verilog/rtl/rtl/soc/modules/sram_wrap.sv
@@ -12,7 +12,7 @@
 
 module sram_wrap #(
     parameter SRAM_BASE_ADDR      = 32'h8000_0000,
-    parameter SRAM_NUM_BLOCKS     = 8,
+    parameter SRAM_NUM_BLOCKS     = 6,
     parameter SRAM_BLOCK_SIZE     = 512,
     parameter SRAM_LOG_BLOCK_SIZE = $clog2(SRAM_BLOCK_SIZE),
     parameter SRAM_END_ADDR       = (SRAM_BASE_ADDR + (SRAM_NUM_BLOCKS * SRAM_BLOCK_SIZE)),
@@ -209,42 +209,6 @@ module sram_wrap #(
         .dout1     (sram_i_read_vec[5]) 
     );
 
-    sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram6 (
-    `ifdef USE_POWER_PINS
-        .vccd1(vccd1), // 1.8V
-        .vssd1(vssd1), // Digital ground
-    `endif
-        .clk0      (clk_i),
-        .csb0      (~cs_data[6]),   // Active Low
-        .web0      (~sram_d_we_i),  // Active Low
-        .wmask0    (sram_d_be_i),
-        .addr0     (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
-        .din0      (sram_d_wdata_i), 
-        .dout0     (sram_d_read_vec[6]), 
-        .clk1      (clk_i),
-        .csb1      (~cs_inst[6]),    // Active Low
-        .addr1     (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]), 
-        .dout1     (sram_i_read_vec[6]) 
-    );
-
-    sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram7 (
-    `ifdef USE_POWER_PINS
-        .vccd1(vccd1), // 1.8V
-        .vssd1(vssd1), // Digital ground
-    `endif
-        .clk0      (clk_i),
-        .csb0      (~cs_data[7]),   // Active Low
-        .web0      (~sram_d_we_i),  // Active Low
-        .wmask0    (sram_d_be_i),
-        .addr0     (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
-        .din0      (sram_d_wdata_i), 
-        .dout0     (sram_d_read_vec[7]), 
-        .clk1      (clk_i),
-        .csb1      (~cs_inst[7]),    // Active Low
-        .addr1     (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]), 
-        .dout1     (sram_i_read_vec[7]) 
-    );
-
 
 `ifdef VERILATOR
     logic [31:0] _unused;