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Merge pull request #34 from Cal-Poly-RAMP/qspi-pass-thru
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QSPI Pass Thru Programming and Other Minor Adjustments
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@Peter-Herrmann
Peter-Herrmann authored Nov 8, 2023
2 parents 47708f7 + 266cdb3 commit 886518c
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223 changes: 176 additions & 47 deletions README.md
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# Cal Poly CARP SoC
<!-- omit in toc -->
# Cal Poly CARP SOC
[![CI](https://github.com/Cal-Poly-RAMP/tapeout-ci-2311/actions/workflows/user_project_ci.yml/badge.svg)](https://github.com/Cal-Poly-RAMP/tapeout-ci-2311/actions/workflows/user_project_ci.yml)

# Memory Map
- [Architecture Overview](#architecture-overview)
- [OBI Bus And Peripherals](#obi-bus-and-peripherals)
- [Memory Map](#memory-map)
- [Boot ROM and Boot Configs](#boot-rom-and-boot-configs)
- [XIP QSPI Flash Controller (QSPI\_1)](#xip-qspi-flash-controller-qspi_1)
- [Monitor Interrupt Generator](#monitor-interrupt-generator)
- [Wishbone-OBI Bridge](#wishbone-obi-bridge)
- [OBI Bus Protocol](#obi-bus-protocol)
- [IO Assignment](#io-assignment)
- [GPIO Pins](#gpio-pins)
- [Logic Analyzer Pins](#logic-analyzer-pins)
- [Logic Analyzer Sample Channels](#logic-analyzer-sample-channels)
- [Pin Descriptions (QFN64 9x9 0.5)](#pin-descriptions-qfn64-9x9-05)

| Address Range | Section |
| :--- | :---:|
| 0x0000_0000<br>0x0000_0FFF | Bootloader |
| 0x0000_1000<br>0x0FFF_FFFF | -- |
| 0x1000_0000<br>0x1000_1FFF | Peripheral Register File |
| 0x1000_1000<br>0x1FFF_FFFF | -- |
| 0x2000_0000<br>0x3FFF_FFFF | 512Mb Flash |
| 0x4000_0000<br>0x7FFF_FFFF | -- |
| 0x8000_0000<br>0x8000_FFFF | SRAM |
| 0x8001_0000<br>0xFFFF_FFFF | -- |
# Architecture Overview

# Memory Interconnects
![CARP drawio](https://github.com/Cal-Poly-RAMP/tapeout-ci-2311/assets/114958111/da811b77-7d82-4069-ad05-54c06919866c)

## OBI Subset
The CARP SOC is composed of 2 RISC-V RV32I processors, a primary processor (the "CARP Core") and a processor that manages and monitors the CARP Core (the "Monitor Core"). The processors each have their own address space, volatile and (off-chip) non-volatile memory, clocks, resets, and peripherals. The Monitor Core and its peripherals have their documentation [here](https://caravel-harness.readthedocs.io/en/latest/getting-started.html), while the CARP Core and its peripherals are documented below.

The main memory interconnect used on the SoC is a subset of OpenHW Group's Open Bus Interface (OBI). The subset we are using is the same subset used by OpenHW Groups's RI5CY Core, and its behavior is fully described in the OBI-1 specification. The specific signals are enumerated below:
# OBI Bus And Peripherals

## Memory Map

The main memory interconnect used on the SoC is a subset of OpenHW Group's Open Bus Interface (OBI). The subset we are using is the same subset used by OpenHW Groups's RI5CY Core, and its behavior is fully described in the OBI-1 specification.

| Start Address | End Address | Section |
| :--- | :--- | :---:|
| 0x0000_0000 | 0x0000_0FFF | Bootloader |
| 0x0000_1000 | 0x0FFF_FFFF | -- |
| 0x1000_0000 | 0x1000_1FFF | Peripheral Register File |
| 0x1000_1000 | 0x1FFF_FFFF | -- |
| 0x2000_0000 | 0x3FFF_FFFF | 512Mb Flash |
| 0x4000_0000 | 0x7FFF_FFFF | -- |
| 0x8000_0000 | 0x8000_4FFF | 20 kB SRAM |
| 0x8000_5000 | 0xEFFF_FFFF | -- |
| 0xF000_0000 | 0xF000_0003 | Monitor Interrupt Generator |
| 0xF000_0004 | 0xFFFF_FFFF | -- |

### Boot ROM and Boot Configs

On boot, the core resets the program counter to an address based on the boot_sel input.

| `boot_sel` | `copy_boot_sel` | Program Counter Reset Address | Function |
| :---: | :---: | :---: | :--- |
| `0` | `0` | `0x0000_0000` | Copies 512 words from QSPI (starting from `0x2000_0000` into SRAM), then jumps to SRAM at `0x8000_0000`. |
| `0` | `1` | `0x0000_0000` | Jumps to QSPI at `0x2000_0000` and begins executing in place. |
| `1` | x | `0x8000_0000` | Starts execution from the internal SRAM. <br> This assumes that the caravel has loaded a program into the SRAM prior to startup. |

### XIP QSPI Flash Controller (QSPI_1)

The QSPI controller at `0x2000_0000` can support up to 512MB external QSPI memory. This flash can be programmed via the housekeeping SPI (SPI_0) in pass-thru mode. There is a 32 bit control register located at address `0x3FFF_FFFF`, described below.

| Bit(s) | Description |
| -----: | --------------------------------------------------------- |
| 31 | MEMIO Enable (reset=1, set to 0 to bit bang SPI commands) |
| 30:23 | Reserved (read 0) |
| 22 | DDR Enable bit (reset=0) |
| 21 | QSPI Enable bit (reset=0) |
| 20 | CRM Enable bit (reset=0) |
| 19:16 | Read latency (dummy) cycles (reset=8) |
| 15:12 | Reserved (read 0) |
| 11:8 | IO Output enable bits in bit bang mode |
| 7:6 | Reserved (read 0) |
| 5 | Chip select (CS) line in bit bang mode |
| 4 | Serial clock line in bit bang mode |
| 3:0 | IO data bits in bit bang mode |

The following settings for CRM/DDR/QSPI modes are valid:

| CRM | QSPI | DDR | Read Command Byte | Mode Byte |
| :-: | :--: | :-: | :-------------------- | :-------: |
| 0 | 0 | 0 | 03h Read | N/A |
| 0 | 0 | 1 | BBh Dual I/O Read | `0xFF` |
| 1 | 0 | 1 | BBh Dual I/O Read | `0xA5` |
| 0 | 1 | 0 | EBh Quad I/O Read | `0xFF` |
| 1 | 1 | 0 | EBh Quad I/O Read | `0xA5` |
| 0 | 1 | 1 | EDh DDR Quad I/O Read | `0xFF` |
| 1 | 1 | 1 | EDh DDR Quad I/O Read | `0xA5` |

### Monitor Interrupt Generator

There is a 3 bit interrupt vector for the Monitor Core that can be generated by the CARP SOC by writing to address `0xF000_0000`. The two least significant bits are generated by the two least significant bits of the write data, and the third bit of the interrupt vector is reserved for hardware-generated interrupts

| irq[2] | irq[1] | irq[0] |
| :--- | :--- | :--- |
| Hardware Error | Write Data bit 1 | Write Data bit 0 |

## Wishbone-OBI Bridge

The wishbone port on the SOC allows the Monitor Core to read and write to the CARP Core's SRAM, as long as the `wishbone enable` control is set (see Logic Analyzer). The SRAM is located at address `0x3000_0000` in the wishbone address space. The Wishbone-OBI bridge handles clock domain crossing, protocol conversion, and address translation.

## OBI Bus Protocol

The specific signals are enumerated below:

| Pin Name | Pin Count | Direction | Description |
|-----------|:---------:|-------------------------|----------------------------------------------------------------|
Expand All @@ -31,24 +109,6 @@ The main memory interconnect used on the SoC is a subset of OpenHW Group's Open
| rvalid | 1 | Memory -> Controller | Asserted by the memory system to signal valid read data. The read response is completed on the first rising clock edge when rvalid is asserted. rdata must be valid as long as rvalid is high. |
| rdata | 32 | Memory -> Controller | Read data input to the controller from the memory system |

## Wishbone

The caravel wrapper uses a Wishbone bus the operates at a faster clock speed than the SOC. The wishbone port on the SOC allows the caravel to read and write to SRAM, as long as the wishbone enable control is set (see Logic Analyzer)
.
# Memory Devices

## Boot ROMs

On boot, the core resets the program counter to an address based on the boot_sel input.

| `boot_sel` | Program Counter Reset Address | Function |
| :---: | :---: | :--- |
| `0` | `0x0000_0000` | Runs the default bootloader from ROM |
| `1` | `0x8000_0000` | Starts execution from the internal SRAM. <br> This assumes that the caravel has loaded a program into the SRAM prior to startup. |

## XIP Flash Controller

In order to run programs off of an external flash, it is ideal that we use an eXecute In Place (XIP) flash controller. This can be done through software in the bootloader, or through hardware by an XIP flash controller. The XIP controllers we have chosen are read-only, however, so this flash interface is essentialy ROM.

# IO Assignment

Expand All @@ -58,20 +118,20 @@ There are 38 user-programmable IO pins:

| Pin # | Input Pin | Output Pin | Output Enable | Description |
| --- | --- | --- | --- | --- |
| 0 | reserved | reserved | reserved | reserved |
| 1 | reserved | reserved | reserved | reserved |
| 2 | reserved | reserved | reserved | reserved |
| 3 | reserved | reserved | reserved | reserved |
| 4 | reserved | reserved | reserved | reserved |
| 5 | boot_mode | x | x | 1 = copy 512 words from flash to SRAM and jump to SRAM. 0 = jump to flash. |
| 6 | boot_sel_hard | x | x | Hard select for the bootloader. (see Boot ROMs) |
| 7 | rst_btn_n | x | x | Hard reset input, such as for a reset button (active low) |
| 8 | x | o_qspi_sck | 0 | QSPI clock |
| 9 | x | o_qspi_cs_n | 0 | QSPI chip select (active low) |
| 10 | i_qspi_dat[0] | o_qspi_dat[0] | Determined by `o_qspi_mod` | QSPI data bit 0 |
| 11 | i_qspi_dat[1] | o_qspi_dat[1] | Determined by `o_qspi_mod` | QSPI data bit 1 |
| 12 | i_qspi_dat[2] | o_qspi_dat[2] | Determined by `o_qspi_mod` | QSPI data bit 2 |
| 13 | i_qspi_dat[3] | o_qspi_dat[3] | Determined by `o_qspi_mod` | QSPI data bit 3 |
| 0 | JTAG | x | x | reserved |
| 1 | x | SPI_0_SDO | 1 | SPI 0 (Housekeeping SPI) |
| 2 | SPI_0_SDI | x | 0 | SPI 0 (Housekeeping SPI) |
| 3 | SPI_0_CSB | x | 0 | SPI 0 (Housekeeping SPI) |
| 4 | SPI_0_SCK | x | 0 | SPI 0 (Housekeeping SPI) |
| 5 | `copy_boot_sel` | x | x | 1 = copy 512 words from flash to SRAM and jump to SRAM. 0 = jump to flash. |
| 6 | `boot_sel` | x | x | Hard select for the bootloader. (see Boot ROMs) |
| 7 | `rst_hard_n` | x | x | Hard reset input, such as for a reset button (active low) |
| 8 | x | `o_qspi_cs_n` | 0 | QSPI chip select (active low) |
| 9 | x | `o_qspi_sck` | 0 | QSPI clock |
| 10 | `i_qspi_dat[0]` | `o_qspi_dat[0]` | Determined by `o_qspi_mod` | QSPI data bit 0 |
| 11 | `i_qspi_dat[1]` | `o_qspi_dat[1]` | Determined by `o_qspi_mod` | QSPI data bit 1 |
| 12 | `i_qspi_dat[2`] | `o_qspi_dat[2]` | Determined by `o_qspi_mod` | QSPI data bit 2 |
| 13 | `i_qspi_dat[3]` | `o_qspi_dat[3]` | Determined by `o_qspi_mod` | QSPI data bit 3 |
| 14 | | | | (Peripherals) |
| 15 | | | | (Peripherals) |
| 16 | | | | (Peripherals) |
Expand Down Expand Up @@ -162,3 +222,72 @@ There are 128 logic analyzer io pins controllable from the caravel.
| 125 | `mem_err_int` | `mcause[5]` | `mcause[13]` | `mcause[21]` | `mcause[29]` | `rf_wr_data[30]` | - | - |
| 126 | `boot_sel` | `mcause[6]` | `mcause[14]` | `mcause[22]` | `mcause[30]` | `rf_wr_data[31]` | - | - |
| 127 | `copy_boot_sel` | `mcause[7]` | `mcause[15]` | `mcause[23]` | `mcause[31]` | `rf_wr_en` | - | - |

## Pin Descriptions (QFN64 9x9 0.5)

| Pin | Name | Description | Voltage min | Voltage nom | Voltage max |
| --- | --------- | -------------------------- | ----------- | --------------------- | ----------- |
| 1 | vssa2 | Analog Ground | | 0 | |
| 2 | io25 | IO 25 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 3 | io26 | IO 26 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 4 | io27 | IO 27 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 5 | io28 | IO 28 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 6 | io29 | IO 29 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 7 | io30 | IO 30 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 8 | io31 | IO 31 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 9 | vdda2 | Analog Supply Voltage | | 3.3 | |
| 10 | vssd2 | Digital Ground | | 0 | |
| 11 | io32 | IO 32 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 12 | io33 | IO 33 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 13 | io34 | IO 34 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 14 | io35 | IO 35 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 15 | io36 | IO 36 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 16 | io37 | IO 37 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 17 | vddio1 | IO Pad Supply Voltage | 1.8 | 3.3 | 5 |
| 18 | vccd | Core Voltage | 1.62 | 1.8 | 1.98 |
| 19 | N/C | No connect | | \- | |
| 20 | vssa | Analog Ground | | 0 | |
| 21 | resetb | Digital Reset (Active Low) | 0 | \> 0.8 \* vddio | vddio |
| 22 | clock | 10 MHz clock | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 23 | vssd | Digital Ground | | 0 | |
| 24 | flash_csb | QSPI_0 Chip Select | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 25 | flash_clk | QSPI_0 Clock | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 26 | flash_io0 | QSPI_0 D0 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 27 | flash_io1 | QSPI_0 D1 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 28 | gpio | Single pin management GPIO | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 29 | vssio | IO Pad Ground | | 0 | |
| 30 | vdda | Analog Supply Voltage | | 3.3 | |
| 31 | io0 | JTAG | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 32 | io1 | SPI_0_SD0 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 33 | io2 | SPI_0_SDI | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 34 | io3 | SPI_0_CSB | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 35 | io4 | SPI_0_SCK | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 36 | io5 | CARP Core Copy Boot Select | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 37 | io6 | CARP Core Boot Select | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 38 | vssa1 | Analog Ground | | 0 | |
| 39 | vssd1 | Digital Ground | | 0 | |
| 40 | vdda1 | Analog Supply Voltage | | 3.3 | |
| 41 | io7 | CARP Core Hard reset | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 42 | io8 | QSPI_1 Clock | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 43 | io9 | QSPI_1 Chip Select | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 44 | io10 | QSPI_1 D0 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 45 | io11 | QSPI_1 D1 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 46 | io12 | QSPI_1 D2 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 47 | vdda1 | Analog Supply Voltage | | 3.3 | |
| 48 | io13 | QSPI_1 D3 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 49 | vccd1 | Core Voltage | 1.8 | 3.3 | 5 |
| 50 | io14 | IO 14 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 51 | io15 | IO 15 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 52 | vssa1 | Analog Ground | | 0 | |
| 53 | io16 | IO 16 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 54 | io17 | IO 17 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 55 | io18 | IO 18 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 56 | vssio | IO Pad Ground | | 0 | |
| 57 | io19 | IO 19 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 58 | io20 | IO 20 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 59 | io21 | IO 21 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 60 | io22 | IO 22 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 61 | io23 | IO 23 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 62 | io24 | IO 24 | 0 | 0.4 or (0.8 \* vddio) | vddio |
| 63 | vccd2 | Core Voltage | 1.62 | 1.8 | 1.98 |
| 64 | vddio2 | IO Pad Supply Voltage | 1.8 | 3.3 | 5 |
6 changes: 3 additions & 3 deletions verilog/rtl/rtl/soc/soc.sv
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Expand Up @@ -593,8 +593,8 @@ module soc (
gpio_oeb_no[7] = '1;

// QSPI Pins
gpio_o[8] = qspi_sck;
gpio_o[9] = qspi_cs_n;
gpio_o[8] = qspi_cs_n;
gpio_o[9] = qspi_sck;
gpio_o[13:10] = qspi_dat_out;
qspi_dat_in = gpio_i[13:10];
gpio_oeb_no[9:8] = 'b00;
Expand Down Expand Up @@ -743,7 +743,7 @@ module soc (
end

always_comb begin: caravel_interrupt_assignment
caravel_interrupt_o = ((dmem_addr == `CARAVEL_INTR_ADDR) & dmem_we) ? {dmem_wdata[1:0],1'b0} : {2'b0, illegal_access};
caravel_interrupt_o = ((dmem_addr == `CARAVEL_INTR_ADDR) & dmem_we) ? {1'b0, dmem_wdata[1:0]} : {illegal_access, 2'b0};
end
////////////////////////////////
// Unused Signal Terminations //
Expand Down
2 changes: 1 addition & 1 deletion verilog/rtl/user_defines.v
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Expand Up @@ -55,7 +55,7 @@
`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_USER_STD_OUTPUT
`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP
`define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
`define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_USER_STD_OUTPUT
`define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_USER_STD_OUTPUT
`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
Expand Down

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