removing dead code

Cal-Poly-RAMP · Oct 16, 2023 · 4b087dd · 4b087dd
1 parent 186ecb8
commit 4b087dd
Showing 1 changed file with 0 additions and 28 deletions.
diff --git a/openlane/macros/sky130_sram_2kbyte_1rw1r_32x512_8.v b/openlane/macros/sky130_sram_2kbyte_1rw1r_32x512_8.v
@@ -18,10 +18,6 @@ module sky130_sram_2kbyte_1rw1r_32x512_8(
   parameter DATA_WIDTH = 32 ;
   parameter ADDR_WIDTH = 9 ;
   parameter RAM_DEPTH = 1 << ADDR_WIDTH;
-  // FIXME: This delay is arbitrary.
-  parameter DELAY = 3 ;
-  parameter VERBOSE = 1 ; //Set to 0 to only display warnings
-  parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
 
 `ifdef USE_POWER_PINS
     inout vccd1;
@@ -54,13 +50,6 @@ module sky130_sram_2kbyte_1rw1r_32x512_8(
     wmask0_reg = wmask0;
     addr0_reg = addr0;
     din0_reg = din0;
-    // `ifndef SYNTHESIS
-    // #(T_HOLD) dout0 = 32'bx;
-    // `endif
-    // if ( !csb0_reg && web0_reg && VERBOSE ) 
-    //   $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
-    // if ( !csb0_reg && !web0_reg && VERBOSE )
-    //   $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
   end
 
   reg  csb1_reg;
@@ -72,13 +61,6 @@ module sky130_sram_2kbyte_1rw1r_32x512_8(
   begin
     csb1_reg = csb1;
     addr1_reg = addr1;
-    // if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
-    //      $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
-    // `ifndef SYNTHESIS
-    // #(T_HOLD) dout1 = 32'bx;
-    // `endif
-    // if ( !csb1_reg && VERBOSE ) 
-    //   $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
   end
 
 reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
@@ -104,25 +86,15 @@ reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
   always @ (negedge clk0)
   begin : MEM_READ0
     if (!csb0_reg && web0_reg)
-      // Synthesis tools will ignore the delay
-      // `ifndef SYNTHESIS
-      // dout0 <= #(DELAY) mem[addr0_reg];
-      // `else
       dout0 <= mem[addr0_reg];
-      // `endif
   end
 
   // Memory Read Block Port 1
   // Read Operation : When web1 = 1, csb1 = 0
   always @ (negedge clk1)
   begin : MEM_READ1
     if (!csb1_reg)
-      // Synthesis tools will ignore the delay
-      // `ifndef SYNTHESIS
-      // dout1 <= #(DELAY) mem[addr1_reg];
-      // `else
       dout1 <= mem[addr1_reg];
-      // `endif
   end
 
 endmodule