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    • This is a containerized environment containing OSS CAD Suite and the RISC-V Toolchain, used for developing CARP IP.
      Shell
      2000Updated Oct 31, 2024Oct 31, 2024
    • carp_pcb

      Public
      C
      41000Updated Sep 21, 2024Sep 21, 2024
    • .github

      Public
      0000Updated May 17, 2024May 17, 2024
    • SourcePawn
      Apache License 2.0
      11000Updated Feb 18, 2024Feb 18, 2024
    • Python
      Apache License 2.0
      13000Updated Feb 17, 2024Feb 17, 2024
    • BaseJump STL: A Standard Template Library for SystemVerilog
      SystemVerilog
      Other
      99000Updated Feb 17, 2024Feb 17, 2024
    • tapeout-ci-2311

      Public template
      caravel-user repository for November 6, 2023 tapeout
      Verilog
      Apache License 2.0
      1130Updated Feb 1, 2024Feb 1, 2024
    • OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
      Verilog
      Apache License 2.0
      373100Updated Jun 14, 2023Jun 14, 2023
    • A configurable SRAM generator
      Rust
      BSD 3-Clause "New" or "Revised" License
      3000Updated May 16, 2023May 16, 2023
    • qspiflash

      Public
      A set of Wishbone Controlled SPI Flash Controllers
      Verilog
      24000Updated May 12, 2023May 12, 2023
    • C++
      0000Updated Jan 17, 2023Jan 17, 2023
    • ramp-core

      Public
      RAMP's out of order RV32G processor, implemented with PyMTL3
      Python
      0200Updated Dec 28, 2022Dec 28, 2022
    • The SystemVerilog style guide for the RAMP framework.
      0000Updated Oct 13, 2022Oct 13, 2022
    • Website for the RAMP framework
      HTML
      0000Updated Aug 4, 2022Aug 4, 2022