-
Notifications
You must be signed in to change notification settings - Fork 6.5k
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
drivers: i3c: cadence: fix tx_fifo width for target mode on rev_id 1p7 #78520
drivers: i3c: cadence: fix tx_fifo width for target mode on rev_id 1p7 #78520
Conversation
Hello @naveeng1001, and thank you very much for your first pull request to the Zephyr project! |
2144341
to
f966e4f
Compare
f966e4f
to
03cb24c
Compare
03cb24c
to
0a1bc90
Compare
Cadence I3C target FIFO width has been increased to 4 bytes in i3c hardware REV_ID 1.7. Writing 1 byte to 4 byte FIFOs can cause unintentional padding for bytes written from TX threshold interrupt handler. Fixed the target callback to handle tx width of i3c target writes to FIFO, by using run time rev_id check. Signed-off-by: Naveen Gangadharan <[email protected]>
0a1bc90
to
2edecaf
Compare
Hi @naveeng1001! To celebrate this milestone and showcase your contribution, we'd love to award you the Zephyr Technical Contributor badge. If you're interested, please claim your badge by filling out this form: Claim Your Zephyr Badge. Thank you for your valuable input, and we look forward to seeing more of your contributions in the future! 🪁 |
Cadence I3C target FIFO width has been increased to 4 bytes in i3c hardware rev_id 1p7. Writing 1 byte to 4 byte FIFOs can cause unintentional padding for bytes written from TX threshold interrupt handler. Fixed the target callback to handle tx width of i3c target writes to FIFO, by using run time rev_id check.