soc: renesas: ra: ra4m1: Migrate to FSP-based configuration #76794
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soburi
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@soburi , I think you need to brush up the PR. There are some changes for RA2A1 are mixed into.
soburi
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Update done. |
zephyrbot
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area: GPIO
area: Pinctrl
platform: Renesas RA
zephyrbot
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| source = <RA_PLL_SOURCE_MAIN_OSC>; | ||
| div = <RA_PLL_DIV_2>; |
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wrong:
- source: define another clock and make it source using eg
clocks = <&main_osc>; - divider should be given as integer
div = <2>;.
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@duynguyenxa @quytranpzz
Are these properties actually used?
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@soburi , these properties are used to provide information for the bsp_clock_cfg.h in the hal layer:
#define BSP_CFG_PLL_SOURCE \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_2)
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay)
The BSP_CFG_PLL_SOURCE, and BSP_CFG_PLL_DIV BSP will be used in the bsp_clock_init() to configure PLL clock.
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FYI: We can't have HALisms in DT.
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@gmarull , the macro is defined in zephyr main repo, zephyr/include/zephyr/dt-bindings/clock/ra_clock.h
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it still looks wrong, why isn't div = <2>? Are such values encoding what HAL expects?
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@gmarull , sorry for late response, it's expect the value map with HWM here for the pll.
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The root of this problem is that the DeviceTree is a hardware description language,
and how values are handled should not be mixed in here.
In other words, the DeviceTree should be able to describe semantic values; for example, if the division factor is 2, then it should be describable as "2", and it should be up to the implementation side, i.e., the .h or .c file, to convert this to bit notation.
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I splitted out this issue to #78365.
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| pclka: pclka { | ||
| compatible = "renesas,ra-cgc-pclk"; | ||
| clk_div = <RA_SYS_CLOCK_DIV_16>; |
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no underscores in properties please.
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I have created #78097.
I will fix it after this PR is merged.
soc/renesas/ra/ra4m1/Kconfig
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| Enable support for Renesas RA4M1 MCU series |
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| help | |
| Enable support for Renesas RA4M1 MCU series |
Update HAL to improve the BSP clock setting process. Signed-off-by: TOKITA Hiroshi <[email protected]>
Like some other string properties, I will add a derived form to FULL_NAME to make it easier to reference from macros. Signed-off-by: TOKITA Hiroshi <[email protected]>
Adding tests for DT_NODE_FULL_NAME_UNQUOTED(), DT_NODE_FULL_NAME_TOKEN(), and DT_NODE_FULL_NAME_UPPER_TOKEN(). Signed-off-by: TOKITA Hiroshi <[email protected]>
Changes the path name of a DTS node so that it can be used as the stem of a BSP macro. All nodes to be changed are referenced via labels, so only the name is changed. Signed-off-by: TOKITA Hiroshi <[email protected]>
DeviceTree typically references the clock source using the `clocks` property defined in `base.yaml`, so we'll change it to this. Also delete the custom clock source definitions in `renesas,ra-cgc-pclk-block.yaml`, `renesas,ra-cgc-pclk.yaml`, and `renesas,ra-cgc-pll.yaml`. Signed-off-by: TOKITA Hiroshi <[email protected]>
Move the process of replacing numerical values with macros to the header, and set the division ratio in a numeric without using macros in the device tree. Change `clk-div` defined in `renesas,ra-cgc-pclk.yaml` to `div`. Signed-off-by: TOKITA Hiroshi <[email protected]>
Adding the macros `RA_CGC_CLK_SRC` and `RA_CGC_CLK_DIV` that derive the BSP clock settings from the DeviceTree node settings. I also define some aliases to fill in the gaps with the BSP naming conventions. Signed-off-by: TOKITA Hiroshi <[email protected]>
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Change to use FSP to integrate with other Renesas RA series. Signed-off-by: TOKITA Hiroshi <[email protected]>
Since the Option Setting Memory area is set in FSP, the Kconfig value switches between using the FSP implementation or the existing Option Setting Memory implementation. Signed-off-by: TOKITA Hiroshi <[email protected]>
Switch the pinctrl driver to renesas,ra-pinctrl-pfs which can be used with FSP. Signed-off-by: TOKITA Hiroshi <[email protected]>
Switch the clock controller driver to renesas,ra-cgc-pclkblock which can be used with FSP. Signed-off-by: TOKITA Hiroshi <[email protected]>
Update configuration for migrate to FSP Signed-off-by: TOKITA Hiroshi <[email protected]>
Update configuration for migrate to FSP Signed-off-by: TOKITA Hiroshi <[email protected]>
Remove the renesas,ra-pinctrl driver, which is no longer needed after migrating to the FSP-based implementation. Signed-off-by: TOKITA Hiroshi <[email protected]>
Remove the renesas,ra-clock-generation-circuit driver, which is no longer needed after migrating to the FSP-based implementation. Signed-off-by: TOKITA Hiroshi <[email protected]>
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Change to use FSP to integrate with other Renesas RA series.