nrf54h20: add support for fast SPIM12x instances #73545
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Memory region defined in devicetree can have attributes that are not intended to be parsed by MPU library, but might be valid for other components. Signed-off-by: Nikodem Kastelik <[email protected]>
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This memory region is used for not only but also DMA transfers of the fast peripherals. Upstream PR: zephyrproject-rtos/zephyr#73545 Signed-off-by: Nikodem Kastelik <[email protected]>
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Fast SPIM instances must not have CLOCKPIN setting applied to MOSI. Upstream PR: zephyrproject-rtos/zephyr#73545 Signed-off-by: Nikodem Kastelik <[email protected]>
anangl
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…nc test case In test cases checking async API, use async API for both controller and peripheral devices. Upstream PR: zephyrproject-rtos/zephyr#73545 Signed-off-by: Nikodem Kastelik <[email protected]>
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Chip Select signal must be deactivated only after transaction is finalized. In async case this means it cannot be done from `transceive` call context, as this context is left as soon as transfer is initialized. Upstream PR: zephyrproject-rtos/zephyr#73545 Signed-off-by: Nikodem Kastelik <[email protected]>
anangl
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Jun 5, 2024
Updated hal_nordic revision brings update to nrfx SPIM driver, allowing external configuration of ENABLE register needed to mitigate SPI bus glitches when using CTRLSEL pins. Upstream PR: zephyrproject-rtos/zephyr#73545 Signed-off-by: Nikodem Kastelik <[email protected]>
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SPIM12x instances can perform DMA only from memory region that is cacheable by default. SPIM12x instances pins are configured via CTRLSEL mechanism, which prevents the GPIO registers from ensuring correct bus state when peripheral does not drive the bus lines. External configuration of SPIM12x ENABLE register fixes this issue. Upstream PR: zephyrproject-rtos/zephyr#73545 Signed-off-by: Nikodem Kastelik <[email protected]>
anangl
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Jun 5, 2024
… features SPI is now supported on nRF54H20 PPR CPU. Upstream PR: zephyrproject-rtos/zephyr#73545 Signed-off-by: Nikodem Kastelik <[email protected]>
anangl
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Jun 5, 2024
SPIM12x have more capabilities than SPIM13x, so it should be tested separately. Upstream PR: zephyrproject-rtos/zephyr#73545 Signed-off-by: Nikodem Kastelik <[email protected]>
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Jun 5, 2024
anangl
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Jul 1, 2024
Memory region defined in devicetree can have attributes that are not intended to be parsed by MPU library, but might be valid for other components. Upstream PR: zephyrproject-rtos/zephyr#73545 Signed-off-by: Nikodem Kastelik <[email protected]> (cherry picked from commit b5d3b1f)
anangl
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Jul 1, 2024
This memory region is used for not only but also DMA transfers of the fast peripherals. Upstream PR: zephyrproject-rtos/zephyr#73545 Signed-off-by: Nikodem Kastelik <[email protected]> (cherry picked from commit f4ff637)
anangl
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Jul 1, 2024
Fast SPIM instances must not have CLOCKPIN setting applied to MOSI. Upstream PR: zephyrproject-rtos/zephyr#73545 Signed-off-by: Nikodem Kastelik <[email protected]> (cherry picked from commit a313fba)
anangl
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Jul 1, 2024
…nc test case In test cases checking async API, use async API for both controller and peripheral devices. Upstream PR: zephyrproject-rtos/zephyr#73545 Signed-off-by: Nikodem Kastelik <[email protected]> (cherry picked from commit 83acb95)
anangl
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Jul 1, 2024
Chip Select signal must be deactivated only after transaction is finalized. In async case this means it cannot be done from `transceive` call context, as this context is left as soon as transfer is initialized. Upstream PR: zephyrproject-rtos/zephyr#73545 Signed-off-by: Nikodem Kastelik <[email protected]> (cherry picked from commit 14ea490)
anangl
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Jul 1, 2024
Updated hal_nordic revision brings update to nrfx SPIM driver, allowing external configuration of ENABLE register needed to mitigate SPI bus glitches when using CTRLSEL pins. Upstream PR: zephyrproject-rtos/zephyr#73545 Signed-off-by: Nikodem Kastelik <[email protected]> (cherry picked from commit f74e796)
anangl
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Jul 1, 2024
SPIM12x instances can perform DMA only from memory region that is cacheable by default. SPIM12x instances pins are configured via CTRLSEL mechanism, which prevents the GPIO registers from ensuring correct bus state when peripheral does not drive the bus lines. External configuration of SPIM12x ENABLE register fixes this issue. Upstream PR: zephyrproject-rtos/zephyr#73545 Signed-off-by: Nikodem Kastelik <[email protected]> (cherry picked from commit 590a1d1)
anangl
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Jul 1, 2024
… features SPI is now supported on nRF54H20 PPR CPU. Upstream PR: zephyrproject-rtos/zephyr#73545 Signed-off-by: Nikodem Kastelik <[email protected]> (cherry picked from commit 0b44283)
anangl
pushed a commit
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Jul 1, 2024
SPIM12x have more capabilities than SPIM13x, so it should be tested separately. Upstream PR: zephyrproject-rtos/zephyr#73545 Signed-off-by: Nikodem Kastelik <[email protected]> (cherry picked from commit 0741603)
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