STM32: configure wake-up pins with GPIOs from devicetree for exiting Poweroff

drivers/gpio/gpio_stm32.c

@@ -22,11 +22,17 @@
 #include <zephyr/drivers/interrupt_controller/exti_stm32.h>
 #include <zephyr/pm/device.h>
 #include <zephyr/pm/device_runtime.h>
+#include <zephyr/drivers/misc/stm32_wkup_pins/stm32_wkup_pins.h>
+#include <zephyr/dt-bindings/gpio/stm32-gpio.h>
 
 #include "stm32_hsem.h"
 #include "gpio_stm32.h"
 #include <zephyr/drivers/gpio/gpio_utils.h>
 
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(stm32, CONFIG_GPIO_LOG_LEVEL);
+
 /**
  * @brief Common GPIO driver for STM32 MCUs.
  */
@@ -541,6 +547,25 @@ static int gpio_stm32_config(const struct device *dev,
 
 	gpio_stm32_configure_raw(dev, pin, pincfg, 0);
 
+#ifdef CONFIG_STM32_WKUP_PINS
+	if (flags & STM32_GPIO_WKUP) {
+#ifdef CONFIG_POWEROFF
+		struct gpio_dt_spec gpio_dt_cfg = {
+			.port = dev,
+			.pin = pin,
+			.dt_flags = (gpio_dt_flags_t)flags,
+		};
+
+		if (stm32_pwr_wkup_pin_cfg_gpio((const struct gpio_dt_spec *)&gpio_dt_cfg)) {
+			LOG_ERR("Could not configure GPIO %s pin %d as a wake-up source",
+					gpio_dt_cfg.port->name, gpio_dt_cfg.pin);
+		}
+#else
+		LOG_DBG("STM32_GPIO_WKUP flag has no effect when CONFIG_POWEROFF=n");
+#endif /* CONFIG_POWEROFF */
+	}
+#endif /* CONFIG_STM32_WKUP_PINS */
+
 	/* Release clock only if pin is disconnected */
 	if (((flags & GPIO_OUTPUT) == 0) && ((flags & GPIO_INPUT) == 0)) {
 		err = pm_device_runtime_put(dev);

dts/arm/st/l4/stm32l4.dtsi

@@ -17,6 +17,7 @@
 #include <zephyr/dt-bindings/dma/stm32_dma.h>
 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
 #include <zephyr/dt-bindings/reset/stm32g4_l4_5_reset.h>
+#include <zephyr/dt-bindings/power/stm32_pwr.h>
 #include <freq.h>
 
 / {
@@ -469,6 +470,39 @@
 				 <&rcc STM32_SRC_MSI CLK48_SEL(3)>;
 			status = "disabled";
 		};
+
+		pwr: power@40007000 {
+			compatible = "st,stm32-pwr";
+			reg = <0x40007000 0x400>; /* PWR register bank */
+			status = "disabled";
+
+			wkup-pins-nb = <5>; /* 5 system wake-up pins */
+			wkup-pins-pol;
+			wkup-pins-pupd;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			wkup-pin@1 {
+				reg = <0x1>;
+			};
+
+			wkup-pin@2 {
+				reg = <0x2>;
+			};
+
+			wkup-pin@3 {
+				reg = <0x3>;
+			};
+
+			wkup-pin@4 {
+				reg = <0x4>;
+			};
+
+			wkup-pin@5 {
+				reg = <0x5>;
+			};
+		};
 	};
 
 	die_temp: dietemp {

dts/arm/st/l4/stm32l4r5Xi.dtsi

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018 Pushpal Sidhu
+ * Copyright (c) 2024 STMicroelectronics
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,3 +17,25 @@
 		};
 	};
 };
+
+&pwr {
+	wkup-pin@1 {
+		wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>;
+	};
+
+	wkup-pin@2 {
+		wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_SRC_0>;
+	};
+
+	wkup-pin@3 {
+		wkup-gpios = <&gpioe 6 STM32_PWR_WKUP_PIN_SRC_0>;
+	};
+
+	wkup-pin@4 {
+		wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_SRC_0>;
+	};
+
+	wkup-pin@5 {
+		wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_SRC_0>;
+	};
+};

dts/arm/st/u5/stm32u5.dtsi

@@ -19,6 +19,7 @@
 #include <zephyr/dt-bindings/dma/stm32_dma.h>
 #include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>
 #include <zephyr/dt-bindings/adc/stm32u5_adc.h>
+#include <zephyr/dt-bindings/power/stm32_pwr.h>
 #include <freq.h>
 
 / {
@@ -841,6 +842,76 @@
 			};
 		};
 
+		pwr: power@46020800 {
+			compatible = "st,stm32-pwr";
+			reg = <0x46020800 0x400>; /* PWR register bank */
+			status = "disabled";
+
+			wkup-pins-nb = <8>; /* 8 system wake-up pins */
+			wkup-pin-srcs = <3>; /* 3 gpio sources associated with each wkup pin */
+			wkup-pins-pol;
+			wkup-pins-pupd;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			wkup-pin@1 {
+				reg = <0x1>;
+				wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>,
+					     <&gpiob 2 STM32_PWR_WKUP_PIN_SRC_1>,
+					     <&gpioe 4 STM32_PWR_WKUP_PIN_SRC_2>;
+			};
+
+			wkup-pin@2 {
+				reg = <0x2>;
+				wkup-gpios = <&gpioa 4 STM32_PWR_WKUP_PIN_SRC_0>,
+					     <&gpioc 13 STM32_PWR_WKUP_PIN_SRC_1>,
+					     <&gpioe 5 STM32_PWR_WKUP_PIN_SRC_2>;
+			};
+
+			wkup-pin@3 {
+				reg = <0x3>;
+				wkup-gpios = <&gpioe 6 STM32_PWR_WKUP_PIN_SRC_0>,
+					     <&gpioa 1 STM32_PWR_WKUP_PIN_SRC_1>,
+					     <&gpiob 6 STM32_PWR_WKUP_PIN_SRC_2>;
+			};
+
+			wkup-pin@4 {
+				reg = <0x4>;
+				wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_SRC_0>,
+					     <&gpiob 1 STM32_PWR_WKUP_PIN_SRC_1>,
+					     <&gpiob 7 STM32_PWR_WKUP_PIN_SRC_2>;
+			};
+
+			wkup-pin@5 {
+				reg = <0x5>;
+				wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_SRC_0>,
+					     <&gpioa 3 STM32_PWR_WKUP_PIN_SRC_1>,
+					     <&gpiob 8 STM32_PWR_WKUP_PIN_SRC_2>;
+			};
+
+			wkup-pin@6 {
+				reg = <0x6>;
+				wkup-gpios = <&gpiob 5 STM32_PWR_WKUP_PIN_SRC_0>,
+					     <&gpioa 5 STM32_PWR_WKUP_PIN_SRC_1>,
+					     <&gpioe 7 STM32_PWR_WKUP_PIN_SRC_2>;
+			};
+
+			wkup-pin@7 {
+				reg = <0x7>;
+				wkup-gpios = <&gpiob 15 STM32_PWR_WKUP_PIN_SRC_0>,
+					     <&gpioa 6 STM32_PWR_WKUP_PIN_SRC_1>,
+					     <&gpioe 8 STM32_PWR_WKUP_PIN_SRC_2>;
+			};
+
+			wkup-pin@8 {
+				reg = <0x8>;
+				wkup-gpios = <&gpiof 2 STM32_PWR_WKUP_PIN_SRC_0>,
+					     <&gpioa 7 STM32_PWR_WKUP_PIN_SRC_1>,
+					     <&gpiob 10 STM32_PWR_WKUP_PIN_SRC_2>;
+			};
+		};
+
 	};
 
 	swj_port: swj_port {

dts/arm/st/wb/stm32wb.dtsi

@@ -16,6 +16,7 @@
 #include <zephyr/dt-bindings/dma/stm32_dma.h>
 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
 #include <zephyr/dt-bindings/reset/stm32wb_l_reset.h>
+#include <zephyr/dt-bindings/power/stm32_pwr.h>
 #include <freq.h>
 
 / {
@@ -512,6 +513,29 @@
 			interrupts = <51 0>;
 			status = "disabled";
 		};
+
+		pwr: power@58000400 {
+			compatible = "st,stm32-pwr";
+			reg = <0x58000400 0x400>; /* PWR register bank */
+			status = "disabled";
+
+			wkup-pins-nb = <5>; /* 5 system wake-up pins */
+			wkup-pins-pol;
+			wkup-pins-pupd;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			wkup-pin@1 {
+				reg = <0x1>;
+				wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>;
+			};
+
+			wkup-pin@4 {
+				reg = <0x4>;
+				wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_SRC_0>;
+			};
+		};
 	};
 
 	die_temp: dietemp {

dts/arm/st/wb/stm32wb55Xg.dtsi

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018 Linaro Limited
+ * Copyright (c) 2024 STMicroelectronics
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,3 +20,20 @@
 		};
 	};
 };
+
+&pwr {
+	wkup-pin@2 {
+		reg = <0x2>;
+		wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_SRC_0>;
+	};
+
+	wkup-pin@3 {
+		reg = <0x3>;
+		wkup-gpios = <&gpioc 12 STM32_PWR_WKUP_PIN_SRC_0>;
+	};
+
+	wkup-pin@5 {
+		reg = <0x5>;
+		wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_SRC_0>;
+	};
+};

dts/arm/st/wl/stm32wl.dtsi

@@ -15,6 +15,7 @@
 #include <zephyr/dt-bindings/dma/stm32_dma.h>
 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
 #include <zephyr/dt-bindings/reset/stm32wb_l_reset.h>
+#include <zephyr/dt-bindings/power/stm32_pwr.h>
 #include <freq.h>
 
 / {
@@ -498,6 +499,34 @@
 			dma-requests= <38>;
 			status = "disabled";
 		};
+
+		pwr: power@58000400 {
+			compatible = "st,stm32-pwr";
+			reg = <0x58000400 0x400>; /* PWR register bank */
+			status = "disabled";
+
+			wkup-pins-nb = <3>; /* 3 system wake-up pins */
+			wkup-pins-pol;
+			wkup-pins-pupd;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			wkup-pin@1 {
+				reg = <0x1>;
+				wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>;
+			};
+
+			wkup-pin@2 {
+				reg = <0x2>;
+				wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_SRC_0>;
+			};
+
+			wkup-pin@3 {
+				reg = <0x3>;
+				wkup-gpios = <&gpiob 3 STM32_PWR_WKUP_PIN_SRC_0>;
+			};
+		};
 	};
 
 	die_temp: dietemp {

dts/bindings/power/st,stm32-pwr.yaml

@@ -0,0 +1,67 @@
+# Copyright (c) 2023 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 power controller
+
+compatible: "st,stm32-pwr"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  wkup-pins-nb:
+    type: int
+    description: |
+      Max nbr of system wake-up pins.
+      For example wkup-pins-nb = <8>; on the stm32u5
+
+  wkup-pin-srcs:
+    type: int
+    description: |
+      Number of wake-up GPIO sources to select from for each wake-up pin.
+      If not specified, that means there is only 1 GPIO source for each
+      wake-up pin.
+
+      For example, each wake-up pin on STM32U5 is associated with
+      4 wake-up sources, 3 of them correspond to GPIOs.
+
+  wkup-pins-pol:
+    type: boolean
+    description: |
+      True if SoC has a wake-up pins polarity config register
+
+  wkup-pins-pupd:
+    type: boolean
+    description: |
+      True if SoC has pull-up/down config register(s) for GPIO ports
+      that are associated with wake-up pins.
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+child-binding:
+  description: |
+    STM32 wake-up pin node.
+
+    All nodes using this binding must be named "wkup-pin@[index]"
+    index starts from 1
+
+  properties:
+    reg:
+      type: array
+      required: true
+      description: Wake-up pin identifier, same as "index" in node name
+
+    wkup-gpios:
+      type: phandle-array
+      description: |
+        Specifies the GPIOs, if any, that are associated with the wake-up pin.
+
+        For example, for GPIO B2 associated with wakeup source 1 on wake-up
+        pin 1 on STM32U5 SoCs:
+        wkup-gpios = <&gpiob 2 STM32_PWR_WKUP_PIN_SRC_1>, <...>;

include/zephyr/drivers/misc/README

@@ -15,3 +15,7 @@ This directory contains header files of the Miscellaneous Drivers.
   layer graphic operations like widgets, shapes, fonts, text, or bitmaps
   rendering. These operations are controlled by a vendor-specific API designed
   for this device.
+
+* STM32 Wake-up Pins
+  STM32 wake-up pins are part of the Power Control (PWR) peripheral.
+  They can be used to wake-up the system from Poweroff through GPIO pins.