soc: intel: Fix problems with the formatter

No functional changes were made in this update. Only code formatting issues were corrected. This commit is necessary to preserve Git history continuity for future changes involving the switch from ace30_ptl to ace30. Signed-off-by: Grzegorz Bernat <[email protected]>
zephyrproject-rtos · Sep 23, 2024 · c8726d5 · c8726d5
1 parent f61b8f9
commit c8726d5
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Showing 4 changed files with 126 additions and 128 deletions.
diff --git a/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_boot.h b/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_boot.h
@@ -6,7 +6,7 @@
 #ifndef ZEPHYR_SOC_INTEL_ADSP_BOOT_H_
 #define ZEPHYR_SOC_INTEL_ADSP_BOOT_H_
 
-#define DSPCS_REG					0x178d00
+#define DSPCS_REG 0x178d00
 
 struct dspcs {
 	/*
@@ -43,22 +43,22 @@ struct dspcs {
 	} bootctl[5];
 };
 
-#define DSPCS_CTL_SPA					BIT(0)
-#define DSPCS_CTL_CPA					BIT(8)
+#define DSPCS_CTL_SPA BIT(0)
+#define DSPCS_CTL_CPA BIT(8)
 
-#define DSPBR_BCTL_BYPROM				BIT(0)
-#define DSPBR_BCTL_WAITIPCG				BIT(16)
-#define DSPBR_BCTL_WAITIPPG				BIT(17)
+#define DSPBR_BCTL_BYPROM   BIT(0)
+#define DSPBR_BCTL_WAITIPCG BIT(16)
+#define DSPBR_BCTL_WAITIPPG BIT(17)
 
-#define DSPBR_BATTR_LPSCTL_RESTORE_BOOT			BIT(12)
-#define DSPBR_BATTR_LPSCTL_HP_CLOCK_BOOT		BIT(13)
-#define DSPBR_BATTR_LPSCTL_LP_CLOCK_BOOT		BIT(14)
-#define DSPBR_BATTR_LPSCTL_L1_MIN_WAY			BIT(15)
-#define DSPBR_BATTR_LPSCTL_BATTR_SLAVE_CORE		BIT(16)
+#define DSPBR_BATTR_LPSCTL_RESTORE_BOOT     BIT(12)
+#define DSPBR_BATTR_LPSCTL_HP_CLOCK_BOOT    BIT(13)
+#define DSPBR_BATTR_LPSCTL_LP_CLOCK_BOOT    BIT(14)
+#define DSPBR_BATTR_LPSCTL_L1_MIN_WAY       BIT(15)
+#define DSPBR_BATTR_LPSCTL_BATTR_SLAVE_CORE BIT(16)
 
-#define DSPBR_WDT_RESUME				BIT(8)
-#define DSPBR_WDT_RESTART_COMMAND			0x76
+#define DSPBR_WDT_RESUME          BIT(8)
+#define DSPBR_WDT_RESTART_COMMAND 0x76
 
 #define DSPCS (*(volatile struct dspcs *)DSPCS_REG)
 
-#endif /* ZEPHYR_SOC_INTEL_ADSP_BOOT_H_ */
+#endif /* ZEPHYR_SOC_INTEL_ADSP_BOOT_H_ */
diff --git a/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_interrupt.h b/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_interrupt.h
@@ -7,35 +7,35 @@
 #define ZEPHYR_SOC_INTEL_ADSP_INTERRUPT_H_
 
 /* Low priority interrupt indices */
-#define ACE_INTL_HIPC	  0
-#define ACE_INTL_SBIPC	  1
-#define ACE_INTL_ML	  2
-#define ACE_INTL_IDCA	  3
-#define ACE_INTL_LPVML	  4
-#define ACE_INTL_SHA	  5
-#define ACE_INTL_L1L2M	  6
-#define ACE_INTL_I2S	  7
-#define ACE_INTL_DMIC	  8
-#define ACE_INTL_SNDW	  9
-#define ACE_INTL_TTS	  10
-#define ACE_INTL_WDT	  11
+#define ACE_INTL_HIPC     0
+#define ACE_INTL_SBIPC    1
+#define ACE_INTL_ML       2
+#define ACE_INTL_IDCA     3
+#define ACE_INTL_LPVML    4
+#define ACE_INTL_SHA      5
+#define ACE_INTL_L1L2M    6
+#define ACE_INTL_I2S      7
+#define ACE_INTL_DMIC     8
+#define ACE_INTL_SNDW     9
+#define ACE_INTL_TTS      10
+#define ACE_INTL_WDT      11
 #define ACE_INTL_HDAHIDMA 12
 #define ACE_INTL_HDAHODMA 13
 #define ACE_INTL_HDALIDMA 14
 #define ACE_INTL_HDALODMA 15
-#define ACE_INTL_I3C	  16
-#define ACE_INTL_GPDMA	  17
-#define ACE_INTL_PWM	  18
-#define ACE_INTL_I2C	  19
-#define ACE_INTL_SPI	  20
-#define ACE_INTL_UART	  21
-#define ACE_INTL_GPIO	  22
-#define ACE_INTL_UAOL	  23
-#define ACE_INTL_IDCB	  24
-#define ACE_INTL_DCW	  25
-#define ACE_INTL_DTF	  26
-#define ACE_INTL_FLV	  27
-#define ACE_INTL_DPDMA	  28
+#define ACE_INTL_I3C      16
+#define ACE_INTL_GPDMA    17
+#define ACE_INTL_PWM      18
+#define ACE_INTL_I2C      19
+#define ACE_INTL_SPI      20
+#define ACE_INTL_UART     21
+#define ACE_INTL_GPIO     22
+#define ACE_INTL_UAOL     23
+#define ACE_INTL_IDCB     24
+#define ACE_INTL_DCW      25
+#define ACE_INTL_DTF      26
+#define ACE_INTL_FLV      27
+#define ACE_INTL_DPDMA    28
 
 /* Device interrupt control for the low priority interrupts.  It
  * provides per-core masking and status checking: ACE_DINT is an array
@@ -71,18 +71,18 @@ struct ace_dint {
  */
 #define DXHIPCIE_REG 0x91040
 
-#define ACE_DINT	     ((volatile struct ace_dint *)DXHIPCIE_REG)
+#define ACE_DINT             ((volatile struct ace_dint *)DXHIPCIE_REG)
 #define XTENSA_IRQ_NUM_MASK  0xff
 #define XTENSA_IRQ_NUM_SHIFT 0
 
-#define XTENSA_IRQ_NUMBER(_irq)	  ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
+#define XTENSA_IRQ_NUMBER(_irq)   ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
 /* Convert between IRQ_CONNECT() numbers and ACE_INTL_* interrupts */
-#define ACE_IRQ_NUM_SHIFT	  8
-#define ACE_IRQ_NUM_MASK	  0xFFU
+#define ACE_IRQ_NUM_SHIFT         8
+#define ACE_IRQ_NUM_MASK          0xFFU
 #define ACE_IRQ_FROM_ZEPHYR(_irq) (((_irq >> ACE_IRQ_NUM_SHIFT) & ACE_IRQ_NUM_MASK) - 1)
 
 #define ACE_INTC_IRQ DT_IRQN(DT_NODELABEL(ace_intc))
 #define ACE_IRQ_TO_ZEPHYR(_irq)                                                                    \
 	((((_irq + 1) & ACE_IRQ_NUM_MASK) << ACE_IRQ_NUM_SHIFT) + ACE_INTC_IRQ)
 
-#endif
+#endif
diff --git a/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_ipc_regs.h b/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_ipc_regs.h
@@ -44,8 +44,8 @@ struct intel_adsp_ipc {
  * This clears BUSY on the other side of the connection in IDR register.
  */
 #define INTEL_ADSP_IPC_ACE1X_TDA_DONE 0
-#define INTEL_ADSP_IPC_BUSY BIT(31)
-#define INTEL_ADSP_IPC_DONE BIT(31)
+#define INTEL_ADSP_IPC_BUSY           BIT(31)
+#define INTEL_ADSP_IPC_DONE           BIT(31)
 
 #define INTEL_ADSP_IPC_CTL_TBIE BIT(0)
 #define INTEL_ADSP_IPC_CTL_IDIE BIT(1)
@@ -80,4 +80,4 @@ struct ace_idc {
  */
 #define IDC ((volatile struct ace_idc *)INTEL_ADSP_IDC_REG_ADDRESS)
 
-#endif /* ZEPHYR_SOC_INTEL_ADSP_ACE_IPC_REGS_H */
+#endif /* ZEPHYR_SOC_INTEL_ADSP_ACE_IPC_REGS_H */
diff --git a/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_shim.h b/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_shim.h
@@ -17,12 +17,12 @@
  * and clock control operation for DSP FW.
  */
 struct ace_dfpmcch {
-	uint32_t dfspsreq;	/* Offset: 0x00 */
+	uint32_t dfspsreq; /* Offset: 0x00 */
 	uint32_t _unused0[3];
-	uint32_t dfspsrsp;	/* Offset: 0x10 */
+	uint32_t dfspsrsp; /* Offset: 0x10 */
 	uint32_t _unused1[1];
-	uint32_t svcfg;		/* Offset: 0x18 */
-	uint32_t dfltrc;	/* Offset: 0x1c */
+	uint32_t svcfg;  /* Offset: 0x18 */
+	uint32_t dfltrc; /* Offset: 0x1c */
 	uint32_t _unused2[8];
 };
 
@@ -34,77 +34,76 @@ struct ace_dfpmcch {
  * and clock control operation for DSP FW.
  */
 struct ace_dfpmccu {
-	uint32_t dfpmccap;	/* Offset: 0x00 */
-	uint32_t dfhrosccf;	/* Offset: 0x04 */
-	uint32_t dfxosccf;	/* Offset: 0x08 */
-	uint32_t dflrosccf;	/* Offset: 0x0c */
-	uint32_t dfsiorosccf;	/* Offset: 0x10 */
-	uint32_t dfhsiorosccf;	/* Offset: 0x14 */
-	uint32_t dfipllrosccf;	/* Offset: 0x18 */
-	uint32_t dfirosccv;	/* Offset: 0x1c */
-	uint32_t dffbrcfd;	/* Offset: 0x20 */
-	uint32_t dfapllptr;	/* Offset: 0x24 */
+	uint32_t dfpmccap;     /* Offset: 0x00 */
+	uint32_t dfhrosccf;    /* Offset: 0x04 */
+	uint32_t dfxosccf;     /* Offset: 0x08 */
+	uint32_t dflrosccf;    /* Offset: 0x0c */
+	uint32_t dfsiorosccf;  /* Offset: 0x10 */
+	uint32_t dfhsiorosccf; /* Offset: 0x14 */
+	uint32_t dfipllrosccf; /* Offset: 0x18 */
+	uint32_t dfirosccv;    /* Offset: 0x1c */
+	uint32_t dffbrcfd;     /* Offset: 0x20 */
+	uint32_t dfapllptr;    /* Offset: 0x24 */
 	uint32_t _unused0[20];
-	uint32_t dfclkctl;	/* Offset: 0x78 */
-	uint32_t dfclksts;	/* Offset: 0x7c */
-	uint32_t dfintclkctl;	/* Offset: 0x80 */
-	uint32_t dfcrosts;	/* Offset: 0x84 */
-	uint32_t dfcrodiv;	/* Offset: 0x88 */
+	uint32_t dfclkctl;    /* Offset: 0x78 */
+	uint32_t dfclksts;    /* Offset: 0x7c */
+	uint32_t dfintclkctl; /* Offset: 0x80 */
+	uint32_t dfcrosts;    /* Offset: 0x84 */
+	uint32_t dfcrodiv;    /* Offset: 0x88 */
 	uint32_t _unused1[1];
-	uint16_t dfpwrctl;	/* Offset: 0x90 */
-	uint16_t dfpwrsts;	/* Offset: 0x92 */
-	uint16_t dfpwrctl2;	/* Offset: 0x94 */
-	uint16_t dfpwrsts2;	/* Offset: 0x96 */
-	uint32_t dflpsdmas0;	/* Offset: 0x98 */
-	uint32_t dflpsdmas1;	/* Offset: 0x9c */
+	uint16_t dfpwrctl;   /* Offset: 0x90 */
+	uint16_t dfpwrsts;   /* Offset: 0x92 */
+	uint16_t dfpwrctl2;  /* Offset: 0x94 */
+	uint16_t dfpwrsts2;  /* Offset: 0x96 */
+	uint32_t dflpsdmas0; /* Offset: 0x98 */
+	uint32_t dflpsdmas1; /* Offset: 0x9c */
 	uint32_t _unused3[1];
-	uint32_t dfldoctl;	/* Offset: 0xa4 */
+	uint32_t dfldoctl; /* Offset: 0xa4 */
 	uint32_t _unused4[2];
-	uint32_t dflpsalhsso;	/* Offset: 0xb0 */
-	uint32_t dflpsalhss1;	/* Offset: 0xb4 */
-	uint32_t dflpsalhss2;	/* Offset: 0xb8 */
-	uint32_t dflpsalhss3;	/* Offset: 0xbc */
+	uint32_t dflpsalhsso; /* Offset: 0xb0 */
+	uint32_t dflpsalhss1; /* Offset: 0xb4 */
+	uint32_t dflpsalhss2; /* Offset: 0xb8 */
+	uint32_t dflpsalhss3; /* Offset: 0xbc */
 	uint32_t _unused5[10];
 };
 
 #define ACE_DfPMCCH (*((volatile struct ace_dfpmcch *)DT_REG_ADDR(DT_NODELABEL(dfpmcch))))
 #define ACE_DfPMCCU (*((volatile struct ace_dfpmccu *)DT_REG_ADDR(DT_NODELABEL(dfpmccu))))
 
-
-#define ADSP_TTSCAP_OFFSET	0x00
-#define ADSP_RTCWC_OFFSET	0x08
-#define ADSP_DSPWCCTL_OFFSET	0x10
-#define ADSP_DSPWCSTS_OFFSET	0x12
-#define ADSP_DSPWCAV_OFFSET	0x18
-#define ADSP_DSPWC_OFFSET	0x20
-#define ADSP_DSPWCTCS_OFFSET	0x28
-#define ADSP_DSPWCT0C_OFFSET	0x30
-#define ADSP_DSPWCT1C_OFFSET	0x38
-#define ADSP_TSCTRL_OFFSET	0x40
-#define ADSP_ISCS_OFFSET	0x44
-#define ADSP_LSCS_OFFSET	0x48
-#define ADSP_DWCCS_OFFSET	0x50
-#define ADSP_ARTCS_OFFSET	0x58
-#define ADSP_LWCCS_OFFSET	0x60
-#define ADSP_CLTSYNC_OFFSET	0x70
-
-
+#define ADSP_TTSCAP_OFFSET   0x00
+#define ADSP_RTCWC_OFFSET    0x08
+#define ADSP_DSPWCCTL_OFFSET 0x10
+#define ADSP_DSPWCSTS_OFFSET 0x12
+#define ADSP_DSPWCAV_OFFSET  0x18
+#define ADSP_DSPWC_OFFSET    0x20
+#define ADSP_DSPWCTCS_OFFSET 0x28
+#define ADSP_DSPWCT0C_OFFSET 0x30
+#define ADSP_DSPWCT1C_OFFSET 0x38
+#define ADSP_TSCTRL_OFFSET   0x40
+#define ADSP_ISCS_OFFSET     0x44
+#define ADSP_LSCS_OFFSET     0x48
+#define ADSP_DWCCS_OFFSET    0x50
+#define ADSP_ARTCS_OFFSET    0x58
+#define ADSP_LWCCS_OFFSET    0x60
+#define ADSP_CLTSYNC_OFFSET  0x70
 
 #define ADSP_SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c))
 
-
-#define ADSP_SHIM_TSCTRL_NTK       BIT(31)
-#define ADSP_SHIM_TSCTRL_IONTE     BIT(30)
-#define ADSP_SHIM_TSCTRL_DMATS     GENMASK(13, 12)
-#define ADSP_SHIM_TSCTRL_CLNKS     GENMASK(11, 10)
-#define ADSP_SHIM_TSCTRL_HHTSE     BIT(7)
-#define ADSP_SHIM_TSCTRL_LWCS      BIT(6)
-#define ADSP_SHIM_TSCTRL_ODTS      BIT(5)
-#define ADSP_SHIM_TSCTRL_CDMAS     GENMASK(4, 0)
+#define ADSP_SHIM_TSCTRL_NTK   BIT(31)
+#define ADSP_SHIM_TSCTRL_IONTE BIT(30)
+#define ADSP_SHIM_TSCTRL_DMATS GENMASK(13, 12)
+#define ADSP_SHIM_TSCTRL_CLNKS GENMASK(11, 10)
+#define ADSP_SHIM_TSCTRL_HHTSE BIT(7)
+#define ADSP_SHIM_TSCTRL_LWCS  BIT(6)
+#define ADSP_SHIM_TSCTRL_ODTS  BIT(5)
+#define ADSP_SHIM_TSCTRL_CDMAS GENMASK(4, 0)
 
 #endif /* _ASMLANGUAGE */
 
-#define ACE_CLKCTL_WOVCRO    BIT(4)	  /* Request WOVCRO clock */
+#define ACE_CLKCTL_WOVCRO BIT(4) /* Request WOVCRO clock */
+
+#define ACE_CRODIV_CARCDS_MASK GENMASK(7, 0)
+#define ACE_CRODIV_CARCDS(x)   ((x) & ACE_CRODIV_CARCDS_MASK)
 
 #define ACE_CRODIV_CARCDS_MASK	GENMASK(7, 0)
 #define ACE_CRODIV_CARCDS(x)	((x) & ACE_CRODIV_CARCDS_MASK)
@@ -118,31 +117,30 @@ struct ace_dfpmccu {
 #define ADSP_DMWBA_ENABLE   BIT(0)
 #define ADSP_DMWBA_READONLY BIT(1)
 
-#define ADSP_CLKCTL_OSC_SOURCE_MASK  (3<<2)
+#define ADSP_CLKCTL_OSC_SOURCE_MASK  (3 << 2)
 #define ADSP_CLKCTL_OSC_REQUEST_MASK (~BIT_MASK(28))
 
 /** LDO Control */
-#define ADSP_DSPRA_ADDRESS        (0x71A60)
-#define ADSP_LPGPDMACxO_ADDRESS(x) (ADSP_DSPRA_ADDRESS + 0x0000 + 0x0002*(x))
-#define ADSP_DSPIOPO_ADDRESS      (ADSP_DSPRA_ADDRESS + 0x0008)
-#define ADSP_GENO_ADDRESS         (ADSP_DSPRA_ADDRESS + 0x000C)
-#define ADSP_DSPALHO_ADDRESS      (ADSP_DSPRA_ADDRESS + 0x0010)
-
-
-#define DSP_INIT_IOPO   ADSP_DSPIOPO_ADDRESS
-#define IOPO_DMIC_FLAG          BIT(0)
-#define IOPO_DSPKOSEL_FLAG      BIT(1)
-#define IOPO_ANCOSEL_FLAG       BIT(2)
-#define IOPO_DMIXOSEL_FLAG      BIT(3)
-#define IOPO_SLIMOSEL_FLAG      BIT(4)
-#define IOPO_SNDWOSEL_FLAG      BIT(5)
-#define IOPO_SLIMDOSEL_FLAG     BIT(20)
-#define IOPO_I2SSEL_MASK	(0x7 << 0x8)
-
-#define DSP_INIT_GENO   ADSP_GENO_ADDRESS
-#define GENO_MDIVOSEL           BIT(1)
-#define GENO_DIOPTOSEL          BIT(2)
+#define ADSP_DSPRA_ADDRESS         (0x71A60)
+#define ADSP_LPGPDMACxO_ADDRESS(x) (ADSP_DSPRA_ADDRESS + 0x0000 + 0x0002 * (x))
+#define ADSP_DSPIOPO_ADDRESS       (ADSP_DSPRA_ADDRESS + 0x0008)
+#define ADSP_GENO_ADDRESS          (ADSP_DSPRA_ADDRESS + 0x000C)
+#define ADSP_DSPALHO_ADDRESS       (ADSP_DSPRA_ADDRESS + 0x0010)
+
+#define DSP_INIT_IOPO       ADSP_DSPIOPO_ADDRESS
+#define IOPO_DMIC_FLAG      BIT(0)
+#define IOPO_DSPKOSEL_FLAG  BIT(1)
+#define IOPO_ANCOSEL_FLAG   BIT(2)
+#define IOPO_DMIXOSEL_FLAG  BIT(3)
+#define IOPO_SLIMOSEL_FLAG  BIT(4)
+#define IOPO_SNDWOSEL_FLAG  BIT(5)
+#define IOPO_SLIMDOSEL_FLAG BIT(20)
+#define IOPO_I2SSEL_MASK    (0x7 << 0x8)
+
+#define DSP_INIT_GENO  ADSP_GENO_ADDRESS
+#define GENO_MDIVOSEL  BIT(1)
+#define GENO_DIOPTOSEL BIT(2)
 
 #define ADSP_FORCE_DECOUPLED_HDMA_L1_EXIT_BIT BIT(1)
 
-#endif /* ZEPHYR_SOC_INTEL_ADSP_SHIM_H_ */
+#endif /* ZEPHYR_SOC_INTEL_ADSP_SHIM_H_ */