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drivers: pwm: Add support for pch intel blink driver
This patch adds support for PWM blink which is found in intel's PCH hardwares. Signed-off-by: Anisetti Avinash Krishna <[email protected]>
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# Intel Blinky PWM configuration options | ||
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# Copyright (c) 2023 Intel Corporation | ||
# SPDX-License-Identifier: Apache-2.0 | ||
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config PWM_INTEL_BLINKY | ||
bool "Blinky PWM driver" | ||
default y | ||
depends on DT_HAS_INTEL_BLINKY_PWM_ENABLED | ||
help | ||
Enable the INTEL PCH PWM driver found on Intel SoCs |
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/* | ||
* Copyright (c) 2023 Intel Corporation. | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 | ||
*/ | ||
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#define DT_DRV_COMPAT intel_blinky_pwm | ||
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#include <errno.h> | ||
#include <zephyr/device.h> | ||
#include <zephyr/kernel.h> | ||
#include <zephyr/init.h> | ||
#include <zephyr/sys/util.h> | ||
#include <zephyr/devicetree.h> | ||
#include <zephyr/drivers/pwm.h> | ||
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#define PWM_REG_OFFSET PWM_INTEL_CONTROL_OFFSET | ||
#define PWM_ENABLE 0x80000000 | ||
#define PWM_SWUP 0x40000000 | ||
#define PWM_FREQ_INT_SHIFT 8 | ||
#define PWM_BASE_UNIT_FRACTION 14 | ||
#define PWM_FREQ_MAX 0x100 | ||
#define PWM_DUTY_MAX 0x100 | ||
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struct bk_intel_config { | ||
DEVICE_MMIO_NAMED_ROM(reg_base); | ||
uint32_t clock_freq; | ||
uint32_t max_pins; | ||
}; | ||
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struct bk_intel_runtime { | ||
DEVICE_MMIO_NAMED_RAM(reg_base); | ||
}; | ||
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static int bk_intel_set_cycles(const struct device *dev, uint32_t pin, | ||
uint32_t period_cycles, uint32_t pulse_cycles, | ||
pwm_flags_t flags) | ||
{ | ||
struct bk_intel_runtime *rt = dev->data; | ||
const struct bk_intel_config *cfg = dev->config; | ||
uint32_t ret = 0; | ||
uint32_t val = 0; | ||
uint32_t duty; | ||
float period; | ||
float out_freq; | ||
uint32_t base_unit; | ||
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if (pin >= cfg->max_pins) { | ||
ret = -EINVAL; | ||
goto err; | ||
} | ||
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out_freq = cfg->clock_freq / (float) period_cycles; | ||
period = (out_freq * PWM_FREQ_MAX) / cfg->clock_freq; | ||
base_unit = (uint32_t) (period * (1 << PWM_BASE_UNIT_FRACTION)); | ||
duty = (pulse_cycles * PWM_DUTY_MAX) / period_cycles; | ||
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if (duty) { | ||
val = PWM_DUTY_MAX - duty; | ||
val |= (base_unit << PWM_FREQ_INT_SHIFT); | ||
} else { | ||
val = PWM_DUTY_MAX - 1; | ||
} | ||
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val |= PWM_ENABLE | PWM_SWUP; | ||
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if (period >= PWM_FREQ_MAX) { | ||
ret = -EINVAL; | ||
goto err; | ||
} | ||
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if (duty > PWM_DUTY_MAX) { | ||
ret = -EINVAL; | ||
goto err; | ||
} | ||
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sys_write32(val, rt->reg_base + PWM_REG_OFFSET); | ||
err: | ||
return ret; | ||
} | ||
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static int bk_intel_get_cycles_per_sec(const struct device *dev, uint32_t pin, | ||
uint64_t *cycles) | ||
{ | ||
const struct bk_intel_config *cfg = dev->config; | ||
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if (pin >= cfg->max_pins) { | ||
return -EINVAL; | ||
} | ||
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*cycles = cfg->clock_freq; | ||
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return 0; | ||
} | ||
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static const struct pwm_driver_api api_funcs = { | ||
.set_cycles = bk_intel_set_cycles, | ||
.get_cycles_per_sec = bk_intel_get_cycles_per_sec, | ||
}; | ||
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static int bk_intel_init(const struct device *dev) | ||
{ | ||
struct bk_intel_runtime *runtime = dev->data; | ||
const struct bk_intel_config *config = dev->config; | ||
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device_map(&runtime->reg_base, | ||
config->reg_base.phys_addr & ~0xFFU, | ||
config->reg_base.size, | ||
K_MEM_CACHE_NONE); | ||
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return 0; | ||
} | ||
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#define BK_INTEL_DEV_CFG(n) \ | ||
static const struct bk_intel_config bk_cfg_##n = { \ | ||
DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \ | ||
.max_pins = DT_INST_PROP(n, max_pins), \ | ||
.clock_freq = DT_INST_PROP(n, clock_frequency), \ | ||
}; \ | ||
\ | ||
static struct bk_intel_runtime bk_rt_##n; \ | ||
DEVICE_DT_INST_DEFINE(n, &bk_intel_init, NULL, \ | ||
&bk_rt_##n, &bk_cfg_##n, \ | ||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \ | ||
&api_funcs); \ | ||
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DT_INST_FOREACH_STATUS_OKAY(BK_INTEL_DEV_CFG) |
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Original file line number | Diff line number | Diff line change |
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# Copyright (c) 2023 Intel Corporation | ||
# | ||
# SPDX-License-Identifier: Apache-2.0 | ||
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description: Intel blinky PWM | ||
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compatible: "intel,blinky-pwm" | ||
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include: [pwm-controller.yaml, base.yaml] | ||
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properties: | ||
reg: | ||
required: true | ||
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clock-frequency: | ||
type: int | ||
required: true | ||
description: PWM Peripheral Clock frequency in Hz | ||
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max-pins: | ||
type: int | ||
required: true | ||
description: Maximum number of pins supported by platform | ||
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"#pwm-cells": | ||
const: 2 | ||
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pwm-cells: | ||
- channel | ||
- period |
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