boards: shield: add support for stm32f769i_disco board

Add support for STMicroelectronics B-LCD40-DSI1 shiled for stm32f769i_disco board. Default config for lvgl is adjusted to lower value to fix compilation issue on low memory footprint stm32f769i_disco. region `IDT_LIST' overflowed by 121081 bytes bss ' will not fit in region `RAM' ld.bfd: region `RAM' overflowed by 1220664 bytes collect2: error: ld returned 1 exit status Signed-off-by: Saravanan Sekar <[email protected]>
zephyrproject-rtos · Jun 21, 2024 · b343eaf · b343eaf
1 parent 156deb9
commit b343eaf
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Showing 7 changed files with 127 additions and 27 deletions.
diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/Kconfig.defconfig b/boards/shields/st_b_lcd40_dsi1_mb1166/Kconfig.defconfig
@@ -8,19 +8,13 @@ if SHIELD_ST_B_LCD40_DSI1_MB1166 || SHIELD_ST_B_LCD40_DSI1_MB1166_A09
 if LVGL
 
 config STM32_LTDC_FB_NUM
-	default 0
+	default 1
 
 config INPUT
 	default y
 
 config LV_Z_VDB_SIZE
-	default 100
-
-config LV_Z_DOUBLE_VDB
-	default y
-
-config LV_Z_VBD_CUSTOM_SECTION
-	default y
+	default 10
 
 config LV_Z_FULL_REFRESH
 	default y

diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32f769i_disco.conf b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32f769i_disco.conf
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Linumiz
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MEMC=y
+CONFIG_STM32_LTDC_RGB888=y
+CONFIG_HEAP_MEM_POOL_SIZE=65536
+# Initialize after LTDC and MIPI-DSI
+CONFIG_DISPLAY_OTM8009A_INIT_PRIORITY=87
diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32f769i_disco.overlay b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32f769i_disco.overlay
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2024 Linumiz
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/display/panel.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
+
+/ {
+	lvgl_pointer {
+		compatible = "zephyr,lvgl-pointer-input";
+		input = <&ft6202>;
+	};
+
+	chosen {
+		zephyr,display = &ltdc;
+	};
+};
+
+&i2c4 {
+	pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pb7>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	ft6202: ft6202@2a {
+		compatible = "focaltech,ft5336";
+		reg = <0x2a>;
+		int-gpios = <&gpioi 13 0>;
+	};
+};
+
+&ltdc {
+	status = "okay";
+	ext-sdram = <&sdram1>;
+
+	/* orisetech, otm8009a */
+	width = <800>;
+	height = <480>;
+	display-timings {
+		compatible = "zephyr,panel-timing";
+		hsync-active = <0>;
+		vsync-active = <0>;
+		de-active = <0>;
+		pixelclk-active = <0>;
+		hsync-len = <2>;
+		vsync-len = <1>;
+		hback-porch = <34>;
+		vback-porch = <15>;
+		hfront-porch = <34>;
+		vfront-porch = <16>;
+	};
+
+	def-back-color-red = <0>;
+	def-back-color-green = <0>;
+	def-back-color-blue = <0>;
+	pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
+};
+
+&mipi_dsi {
+	status = "okay";
+
+	pll-ndiv = <100>;
+	pll-idf = <5>;
+	pll-odf = <0>;
+
+	vs-active-high;
+	hs-active-high;
+	de-active-high;
+};
+
+&otm8009a {
+	data-lanes = <2>;
+	pixel-format = <MIPI_DSI_PIXFMT_RGB888>;
+	rotation = <90>;
+};
diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166.overlay b/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166.overlay
@@ -4,6 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
+
 &mipi_dsi {
 	otm8009a: otm8009a@0 {
 		status = "okay";

diff --git a/boards/st/stm32f769i_disco/stm32f769i_disco.dts b/boards/st/stm32f769i_disco/stm32f769i_disco.dts
@@ -27,7 +27,7 @@
 	sdram1: sdram@c0000000 {
 		compatible = "zephyr,memory-region", "mmio-sram";
 		device_type = "memory";
-		reg = <0xc0000000 DT_SIZE_M(16)>;
+		reg = <0xc0000000 DT_SIZE_M(128)>;
 		zephyr,memory-region = "SDRAM1";
 		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
 	};
@@ -66,11 +66,6 @@
 		};
 	};
 
-	lvgl_pointer {
-		compatible = "zephyr,lvgl-pointer-input";
-		input = <&ft6202>;
-	};
-
 	aliases {
 		led0 = &red_led_1;
 		led1 = &green_led_2;
@@ -85,6 +80,23 @@
 		zephyr,memory-region = "QSPI_AVAIL";
 		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
 	};
+
+	dsi_lcd_qsh_030: connector_dsi_lcd {
+		compatible = "st,dsi-lcd-qsh-030";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <4 0 &gpioi 13 0>,	/* TOUCH_INT */
+			   <35 0 &gpiod 12 0>,	/* SCLK/MCLK */
+			   <39 0 &gpiod 11 0>,	/* I2S */
+			   <40 0 &gpiob 9 0>,	/* I2C4_SDA */
+			   <44 0 &gpiob 8 0>,	/* I2C4_SCL */
+			   <45 0 &gpioa 8 0>,	/* CEC_CLK */
+			   <47 0 &gpioa 15 0>,	/* CEC */
+			   <49 0 &gpioj 2 0>,	/* DSI_TE */
+			   <53 0 &gpioi 14 0>,	/* LCD_BL_CTRL */
+			   <57 0 &gpioj 15 0>;	/* DSI_RESET */
+	};
 };
 
 &clk_hse {
@@ -97,6 +109,7 @@
 	mul-n = <432>;
 	div-p = <2>;
 	div-q = <9>;
+	div-r = <7>;
 	clocks = <&clk_hse>;
 	status = "okay";
 };
@@ -134,19 +147,6 @@ arduino_serial: &usart6 {};
 	clock-frequency = <I2C_BITRATE_FAST>;
 };
 
-&i2c4 {
-	pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pb7>;
-	pinctrl-names = "default";
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-
-	ft6202: ft6202@2a {
-		compatible = "focaltech,ft5336";
-		reg = <0x2a>;
-		int-gpios = <&gpioi 13 0>;
-	};
-};
-
 &spi2 {
 	pinctrl-0 = <&spi2_nss_pa11 &spi2_sck_pa12 &spi2_miso_pb14 &spi2_mosi_pb15>;
 	pinctrl-names = "default";

diff --git a/dts/arm/st/f7/stm32f765.dtsi b/dts/arm/st/f7/stm32f765.dtsi
@@ -91,6 +91,18 @@
 			status = "disabled";
 		};
 
+		mipi_dsi: dsihost@40016C00 {
+			compatible = "st,stm32-mipi-dsi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40016C00 0x800>;
+			clock-names = "dsiclk", "refclk", "pixelclk";
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x08000000>,
+				 <&rcc STM32_SRC_HSI NO_SEL>,
+				 <&rcc STM32_SRC_PLL_R DSI_SEL(1)>;
+			resets = <&rctl STM32_RESET(APB2, 27U)>;
+			status = "disabled";
+		};
 	};
 
 	smbus4: smbus4 {

diff --git a/dts/bindings/clock/st,stm32f7-pll-clock.yaml b/dts/bindings/clock/st,stm32f7-pll-clock.yaml
@@ -56,3 +56,9 @@ properties:
     description: |
         PLL division factor for PLL48CK
         Valid range: 2 - 15
+
+  div-r:
+    type: int
+    description: |
+        PLL division factor for PLLDSICLK
+        Valid range: 2 - 7