board: MIMXRT1062-FMURT6: Fix the sequence of Enet2 ref clk enablement

This patch sets ENET2 ref clock to be generated by External OSC ENET2 ref clock direction as output ENET2 ref clk frequency to 50MHz Signed-off-by: Sumit Batra <[email protected]>
zephyrproject-rtos · May 31, 2023 · affb7d4 · affb7d4
1 parent c245a16
commit affb7d4
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diff --git a/drivers/ethernet/eth_mcux.c b/drivers/ethernet/eth_mcux.c
@@ -1059,6 +1059,12 @@ static void eth_mcux_init(const struct device *dev)
 			kENET_RxAccelProtoCheckEnabled;
 	}
 
+	/* Set ENET2 ref clock to be generated by External OSC,*/
+	/* direction as output and frequency to 50MHz */
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay)
+	IOMUXC_GPR->GPR1 |= (IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK |
+				IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK);
+#endif
 	ENET_Init(context->base,
 		  &context->enet_handle,
 		  &enet_config,

diff --git a/soc/arm/nxp_imx/rt/soc_rt10xx.c b/soc/arm/nxp_imx/rt/soc_rt10xx.c
@@ -66,7 +66,12 @@ const clock_enet_pll_config_t ethPllConfig = {
 #else
 	.enableClkOutput25M = false,
 #endif
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay)
 	.loopDivider = 1,
+#endif
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay)
+	.loopDivider1 = 1,
+#endif
 };
 #endif