boards: xtensa: Add support for xiao esp32s3

add board support for seeed xiao esp32s3.

Signed-off-by: Jiaxuan Weng <[email protected]>

boards/xtensa/xiao_esp32s3/Kconfig.board

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+# XIAO ESP32S3 board configuration
+
+# Copyright (c) 2023 Seeed Studio inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_XIAO_ESP32S3
+	bool "XIAO ESP32S3 Board"
+	depends on SOC_ESP32S3

boards/xtensa/xiao_esp32s3/Kconfig.defconfig

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+# Copyright (c) 2023 Seeed Studio inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD
+	default "xiao_esp32s3"
+	depends on BOARD_XIAO_ESP32S3
+
+config ENTROPY_GENERATOR
+	default y
+
+config HEAP_MEM_POOL_SIZE
+	default 98304 if WIFI
+	default 40960 if BT
+	default 4096
+
+choice BT_HCI_BUS_TYPE
+	default BT_ESP32 if BT
+endchoice

boards/xtensa/xiao_esp32s3/Kconfig.sysbuild

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+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+choice BOOTLOADER
+	default BOOTLOADER_MCUBOOT
+endchoice
+
+choice BOOT_SIGNATURE_TYPE
+	default BOOT_SIGNATURE_TYPE_NONE
+endchoice

boards/xtensa/xiao_esp32s3/board.cmake

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+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
+  set(OPENOCD OPENOCD-NOTFOUND)
+endif()
+find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
+
+include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/xtensa/xiao_esp32s3/doc/index.rst

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+.. _xiao_esp32s3:
+
+XIAO ESP32S3
+###############
+
+Overview
+********
+
+Seeed Studio XIAO ESP32S3 is an IoT mini development board based on the
+Espressif ESP32-S3 WiFi/Bluetooth dual-mode chip.
+
+For more details see the `Seeed Studio XIAO ESP32S3`_ wiki page.
+
+.. figure:: img/xiao_esp32s3.jpg
+   :align: center
+   :alt: XIAO ESP32S3
+
+   XIAO ESP32S3
+
+Hardware
+********
+
+This board is based on the ESP32-S3 with 8MB of flash, WiFi and BLE support. It
+has an USB-C port for programming and debugging, integrated battery charging
+and an U.FL external antenna connector. It is based on a standard XIAO 14 pin
+pinout.
+
+ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi
+and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor
+(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband,
+RF module, and numerous peripherals.
+
+Supported Features
+==================
+
+Current Zephyr's XIAO ESP32S3 board supports the following features:
+
++------------+------------+-------------------------------------+
+| Interface  | Controller | Driver/Component                    |
++============+============+=====================================+
++------------+------------+-------------------------------------+
+| UART       | on-chip    | serial port                         |
++------------+------------+-------------------------------------+
+| GPIO       | on-chip    | gpio                                |
++------------+------------+-------------------------------------+
+| PINMUX     | on-chip    | pinmux                              |
++------------+------------+-------------------------------------+
+| USB-JTAG   | on-chip    | hardware interface                  |
++------------+------------+-------------------------------------+
+| SPI Master | on-chip    | spi                                 |
++------------+------------+-------------------------------------+
+| Timers     | on-chip    | counter                             |
++------------+------------+-------------------------------------+
+| Watchdog   | on-chip    | watchdog                            |
++------------+------------+-------------------------------------+
+| TRNG       | on-chip    | entropy                             |
++------------+------------+-------------------------------------+
+| LEDC       | on-chip    | pwm                                 |
++------------+------------+-------------------------------------+
+| MCPWM      | on-chip    | pwm                                 |
++------------+------------+-------------------------------------+
+| PCNT       | on-chip    | qdec                                |
++------------+------------+-------------------------------------+
+| GDMA       | on-chip    | dma                                 |
++------------+------------+-------------------------------------+
+
+Connections and IOs
+===================
+
+The board uses a standard XIAO pinout, the default pin mapping is the following:
+
+.. figure:: img/xiao_esp32s3_pinout.jpg
+   :align: center
+   :alt: XIAO ESP32S3 Pinout
+
+   XIAO ESP32S3 Pinout
+
+Prerequisites
+-------------
+
+Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
+below to retrieve those files.
+
+.. code-block:: console
+
+   west blobs fetch hal_espressif
+
+.. note::
+
+   It is recommended running the command above after :file:`west update`.
+
+Building & Flashing
+*******************
+
+ESP-IDF bootloader
+==================
+
+The board is using the ESP-IDF bootloader as the default 2nd stage bootloader.
+It is build as a subproject at each application build. No further attention
+is expected from the user.
+
+MCUboot bootloader
+==================
+
+User may choose to use MCUboot bootloader instead. In that case the bootloader
+must be build (and flash) at least once.
+
+There are two options to be used when building an application:
+
+1. Sysbuild
+2. Manual build
+
+.. note::
+
+   User can select the MCUboot bootloader by adding the following line
+   to the board default configuration file.
+   ```
+   CONFIG_BOOTLOADER_MCUBOOT=y
+   ```
+
+Sysbuild
+========
+
+The sysbuild makes possible to build and flash all necessary images needed to
+bootstrap the board with the EPS32 SoC.
+
+To build the sample application using sysbuild use the command:
+
+.. zephyr-app-commands::
+   :tool: west
+   :app: samples/hello_world
+   :board: xiao_esp32s3
+   :goals: build
+   :west-args: --sysbuild
+   :compact:
+
+By default, the ESP32 sysbuild creates bootloader (MCUboot) and application
+images. But it can be configured to create other kind of images.
+
+Build directory structure created by sysbuild is different from traditional
+Zephyr build. Output is structured by the domain subdirectories:
+
+.. code-block::
+
+  build/
+  ├── hello_world
+  │   └── zephyr
+  │       ├── zephyr.elf
+  │       └── zephyr.bin
+  ├── mcuboot
+  │    └── zephyr
+  │       ├── zephyr.elf
+  │       └── zephyr.bin
+  └── domains.yaml
+
+.. note::
+
+   With ``--sysbuild`` option the bootloader will be re-build and re-flash
+   every time the pristine build is used.
+
+For more information about the system build please read the :ref:`sysbuild` documentation.
+
+Manual build
+============
+
+During the development cycle, it is intended to build & flash as quickly possible.
+For that reason, images can be build one at a time using traditional build.
+
+The instructions following are relevant for both manual build and sysbuild.
+The only difference is the structure of the build directory.
+
+.. note::
+
+   Remember that bootloader (MCUboot) needs to be flash at least once.
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: xiao_esp32s3
+   :goals: build
+
+The usual ``flash`` target will work with the ``xiao_esp32s3`` board
+configuration. Here is an example for the :ref:`hello_world`
+application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: xiao_esp32s3
+   :goals: flash
+
+Open the serial monitor using the following command:
+
+.. code-block:: shell
+
+   west espressif monitor
+
+After the board has automatically reset and booted, you should see the following
+message in the monitor:
+
+.. code-block:: console
+
+   ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
+   Hello World! xiao_esp32s3
+
+Debugging
+*********
+
+ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0.
+Download and install OpenOCD from `OpenOCD`_.
+
+ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary.
+
+Further documentation can be obtained from the SoC vendor in `JTAG debugging
+for ESP32-S3`_.
+
+Here is an example for building the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: xiao_esp32s3
+   :goals: build flash
+
+You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: xiao_esp32s3
+   :goals: debug
+.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/
+.. _`OpenOCD`: https://github.com/openocd-org/openocd
+
+References
+**********
+
+.. target-notes::
+
+.. _`Seeed Studio XIAO ESP32S3`: https://wiki.seeedstudio.com/xiao_esp32s3_getting_started/

boards/xtensa/xiao_esp32s3/seeed_xiao_connector.dtsi

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+/*
+ * Copyright (c) 2023 Seeed Studio inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	xiao_d: connector {
+		compatible = "seeed,xiao-gpio";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpio0 1 0>,	/* D0 */
+				   <1 0 &gpio0 2 0>,	/* D1 */
+				   <2 0 &gpio0 3 0>,	/* D2 */
+				   <3 0 &gpio0 4 0>,	/* D3 */
+				   <4 0 &gpio0 5 0>,	/* D4 */
+				   <5 0 &gpio0 6 0>,	/* D5 */
+				   <6 0 &gpio0 43 0>,	/* D6 */
+				   <7 0 &gpio0 44 0>,	/* D7 */
+				   <8 0 &gpio0 7 0>,	/* D8 */
+				   <9 0 &gpio0 8 0>,	/* D9 */
+				   <10 0 &gpio0 9 0>;	/* D10 */
+	};
+};
+
+xiao_spi: &spi2 {};
+xiao_i2c: &i2c0 {};
+xiao_serial: &uart0 {};

boards/xtensa/xiao_esp32s3/support/openocd.cfg

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+set ESP_RTOS none
+
+source [find interface/esp_usb_jtag.cfg]
+
+source [find target/esp32s3.cfg]
+adapter_khz 5000

boards/xtensa/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi

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+/*
+ * Copyright 2022 Google LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
+#include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h>
+
+&pinctrl {
+	uart0_default: uart0_default {
+		group1 {
+			pinmux = <UART0_TX_GPIO43>;
+			output-high;
+		};
+		group2 {
+			pinmux = <UART0_RX_GPIO44>;
+			bias-pull-up;
+		};
+	};
+
+	spim2_default: spim2_default {
+		group1 {
+			pinmux = <SPIM2_MISO_GPIO8>,
+				 <SPIM2_SCLK_GPIO7>;
+		};
+		group2 {
+			pinmux = <SPIM2_MOSI_GPIO9>;
+			output-low;
+		};
+	};
+
+	i2c0_default: i2c0_default {
+		group1 {
+			pinmux = <I2C0_SDA_GPIO5>,
+				 <I2C0_SCL_GPIO6>;
+			bias-pull-up;
+			drive-open-drain;
+			output-high;
+		};
+	};
+};