tests: microblaze: test specific configuration additions for MicroBlaze

Internal references: FWRIVERHD-5201 Signed-off-by: Alp Sayin <[email protected]>
zephyrproject-rtos · Feb 20, 2023 · 6f89a31 · 6f89a31
1 parent 98d06a3
commit 6f89a31
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Showing 5 changed files with 15 additions and 5 deletions.
diff --git a/tests/kernel/context/src/main.c b/tests/kernel/context/src/main.c
@@ -65,17 +65,19 @@
  * unless TICK_IRQ is defined here for them
  */
 #endif /* defined(CONFIG_ARCH_POSIX) */
+#elif defined(CONFIG_MICROBLAZE) && defined(CONFIG_XLNX_TMRCTR)
+#define TICK_IRQ DT_IRQN(DT_INST(CONFIG_XLNX_TMRCTR_TIMER_INDEX, xlnx_tmrctr))
 #else
 
 extern const int32_t z_sys_timer_irq_for_test;
 #define TICK_IRQ (z_sys_timer_irq_for_test)
 
 #endif
 
-/* Cortex-M1, Nios II, and RISCV without CONFIG_RISCV_HAS_CPU_IDLE
+/* Cortex-M1, Nios II, MicroBlaze, and RISCV without CONFIG_RISCV_HAS_CPU_IDLE
  * do have a power saving instruction, so k_cpu_idle() returns immediately
  */
-#if !defined(CONFIG_CPU_CORTEX_M1) && !defined(CONFIG_NIOS2) && \
+#if !defined(CONFIG_CPU_CORTEX_M1) && !defined(CONFIG_NIOS2) && !defined(CONFIG_MICROBLAZE) &&     \
 	(!defined(CONFIG_RISCV) || defined(CONFIG_RISCV_HAS_CPU_IDLE))
 #define HAS_POWERSAVE_INSTRUCTION
 #endif

diff --git a/tests/kernel/fatal/exception/src/main.c b/tests/kernel/fatal/exception/src/main.c
@@ -84,7 +84,8 @@ void entry_cpu_exception(void *p1, void *p2, void *p3)
 	__asm__ volatile (".word 0x77777777");
 #else
 	/* Triggers usage fault on ARM, illegal instruction on
-	 * xtensa, TLB exception (instruction fetch) on MIPS.
+	 * xtensa, TLB exception (instruction fetch) on MIPS,
+	 * illegal op-code instruction on microblaze
 	 */
 	{
 		volatile long illegal = 0;
@@ -442,6 +443,11 @@ ZTEST(fatal_exception, test_fatal)
 
 static void *fatal_setup(void)
 {
+
+#if defined(CONFIG_MICROBLAZE)
+	microblaze_enable_exceptions();
+#endif
+
 #if defined(CONFIG_DEMAND_PAGING) && \
 	!defined(CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT)
 	uintptr_t pin_addr;

diff --git a/tests/kernel/interrupt/src/interrupt_offload.c b/tests/kernel/interrupt/src/interrupt_offload.c
@@ -91,6 +91,8 @@ void isr_handler(const void *param)
 #elif defined(CONFIG_ARCH_POSIX)
 #define TEST_IRQ_DYN_LINE 5
 
+#elif defined(CONFIG_MICROBLAZE)
+#define TEST_IRQ_DYN_LINE 1
 #else
 #define TEST_IRQ_DYN_LINE 0
 #endif

diff --git a/tests/kernel/mem_protect/stackprot/testcase.yaml b/tests/kernel/mem_protect/stackprot/testcase.yaml
@@ -1,5 +1,5 @@
 tests:
   kernel.memory_protection.stackprot:
-    arch_exclude: nios2 xtensa posix sparc
+    arch_exclude: nios2 xtensa posix sparc microblaze
     tags: kernel userspace
     ignore_faults: true
diff --git a/tests/lib/cpp/libcxx/src/main.cpp b/tests/lib/cpp/libcxx/src/main.cpp
@@ -67,7 +67,7 @@ ZTEST(libcxx_tests, test_make_unique)
 	zassert_equal(make_unique_data::dtors, 1, "dtor count not incremented");
 }
 
-#if defined(CONFIG_CPP_EXCEPTIONS) && !defined(CONFIG_BOARD_M2GL025_MIV)
+#if defined(CONFIG_CPP_EXCEPTIONS) && !defined(CONFIG_BOARD_M2GL025_MIV) && !defined(CONFIG_MICROBLAZE)
 static void throw_exception(void)
 {
 	throw 42;