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Add the MCU STM32L451. Signed-off-by: Benedikt Schmidt <[email protected]>
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/* | ||
* Copyright (c) 2023 SILA Embedded Solutions GmbH | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 | ||
*/ | ||
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#include <st/l4/stm32l4.dtsi> | ||
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/ { | ||
soc { | ||
clocks { | ||
clk_hsi48: clk-hsi48 { | ||
#clock-cells = <0>; | ||
compatible = "fixed-clock"; | ||
clock-frequency = <DT_FREQ_M(48)>; | ||
status = "disabled"; | ||
}; | ||
}; | ||
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pinctrl: pin-controller@48000000 { | ||
gpiod: gpio@48000c00 { | ||
compatible = "st,stm32-gpio"; | ||
gpio-controller; | ||
#gpio-cells = <2>; | ||
reg = <0x48000c00 0x400>; | ||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>; | ||
}; | ||
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gpioe: gpio@48001000 { | ||
compatible = "st,stm32-gpio"; | ||
gpio-controller; | ||
#gpio-cells = <2>; | ||
reg = <0x48001000 0x400>; | ||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>; | ||
}; | ||
}; | ||
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rng: rng@50060800 { | ||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>, | ||
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; | ||
}; | ||
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i2c2: i2c@40005800 { | ||
compatible = "st,stm32-i2c-v2"; | ||
clock-frequency = <I2C_BITRATE_STANDARD>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
reg = <0x40005800 0x400>; | ||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>; | ||
interrupts = <33 0>, <34 0>; | ||
interrupt-names = "event", "error"; | ||
status = "disabled"; | ||
}; | ||
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i2c4: i2c@40008400 { | ||
compatible = "st,stm32-i2c-v2"; | ||
clock-frequency = <I2C_BITRATE_STANDARD>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
reg = <0x40008400 0x400>; | ||
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>; | ||
interrupts = <83 0>, <84 0>; | ||
interrupt-names = "event", "error"; | ||
status = "disabled"; | ||
}; | ||
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spi2: spi@40003800 { | ||
compatible = "st,stm32-spi-fifo", "st,stm32-spi"; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
reg = <0x40003800 0x400>; | ||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>; | ||
interrupts = <36 5>; | ||
status = "disabled"; | ||
}; | ||
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spi3: spi@40003c00 { | ||
compatible = "st,stm32-spi-fifo", "st,stm32-spi"; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
reg = <0x40003c00 0x400>; | ||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>; | ||
interrupts = <51 5>; | ||
status = "disabled"; | ||
}; | ||
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usart3: serial@40004800 { | ||
compatible = "st,stm32-usart", "st,stm32-uart"; | ||
reg = <0x40004800 0x400>; | ||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>; | ||
resets = <&rctl STM32_RESET(APB1L, 18U)>; | ||
interrupts = <39 0>; | ||
status = "disabled"; | ||
}; | ||
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uart4: serial@40004c00 { | ||
compatible = "st,stm32-uart"; | ||
reg = <0x40004c00 0x400>; | ||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>; | ||
resets = <&rctl STM32_RESET(APB1L, 19U)>; | ||
interrupts = <52 0>; | ||
status = "disabled"; | ||
}; | ||
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timers3: timers@40000400 { | ||
compatible = "st,stm32-timers"; | ||
reg = <0x40000400 0x400>; | ||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>; | ||
resets = <&rctl STM32_RESET(APB1L, 1U)>; | ||
interrupts = <29 0>; | ||
interrupt-names = "global"; | ||
st,prescaler = <0>; | ||
status = "disabled"; | ||
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pwm { | ||
compatible = "st,stm32-pwm"; | ||
status = "disabled"; | ||
#pwm-cells = <3>; | ||
}; | ||
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counter { | ||
compatible = "st,stm32-counter"; | ||
status = "disabled"; | ||
}; | ||
}; | ||
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dac1: dac@40007400 { | ||
compatible = "st,stm32-dac"; | ||
reg = <0x40007400 0x400>; | ||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>; | ||
status = "disabled"; | ||
#io-channel-cells = <1>; | ||
}; | ||
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can1: can@40006400 { | ||
compatible = "st,stm32-can"; | ||
reg = <0x40006400 0x400>; | ||
interrupts = <19 0>, <20 0>, <21 0>, <22 0>; | ||
interrupt-names = "TX", "RX0", "RX1", "SCE"; | ||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; //RCC_APB1ENR1_CAN1EN | ||
status = "disabled"; | ||
sjw = <1>; | ||
sample-point = <875>; | ||
}; | ||
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sdmmc1: sdmmc@40012800 { | ||
compatible = "st,stm32-sdmmc"; | ||
reg = <0x40012800 0x400>; | ||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>, | ||
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; | ||
resets = <&rctl STM32_RESET(APB2, 10U)>; | ||
interrupts = <49 0>; | ||
status = "disabled"; | ||
}; | ||
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rtc@40002800 { | ||
bbram: backup_regs { | ||
compatible = "st,stm32-bbram"; | ||
st,backup-regs = <32>; | ||
status = "disabled"; | ||
}; | ||
}; | ||
}; | ||
}; |
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/* | ||
* Copyright (c) 2023 SILA Embedded Solutions GmbH | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 | ||
*/ | ||
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#include <st/l4/stm32l45.dtsi> | ||
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/ { | ||
soc { | ||
compatible = "st,stm32l451", "st,stm32l4", "simple-bus"; | ||
}; | ||
}; |
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/* | ||
* Copyright (c) 2023 SILA Embedded Solutions GmbH | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 | ||
*/ | ||
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#include <mem.h> | ||
#include <st/l4/stm32l451.dtsi> | ||
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/ { | ||
sram0: memory@20000000 { | ||
reg = <0x20000000 DT_SIZE_K(160)>; | ||
}; | ||
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soc { | ||
flash-controller@40022000 { | ||
flash0: flash@8000000 { | ||
reg = <0x08000000 DT_SIZE_K(256)>; | ||
}; | ||
}; | ||
}; | ||
}; |
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/* | ||
* Copyright (c) 2023 SILA Embedded Solutions GmbH | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 | ||
*/ | ||
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#include <mem.h> | ||
#include <st/l4/stm32l451.dtsi> | ||
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/ { | ||
sram0: memory@20000000 { | ||
reg = <0x20000000 DT_SIZE_K(160)>; | ||
}; | ||
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soc { | ||
flash-controller@40022000 { | ||
flash0: flash@8000000 { | ||
reg = <0x08000000 DT_SIZE_K(512)>; | ||
}; | ||
}; | ||
}; | ||
}; |
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