soc: arm: smartbond: Add support for DC/DC converter

This adds support to enable DC/DC converter. Signed-off-by: Andrzej Kaczmarek <[email protected]>
zephyrproject-rtos · Aug 25, 2023 · 1a1db76 · 1a1db76
1 parent 032a4e9
commit 1a1db76
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diff --git a/soc/arm/renesas_smartbond/da1469x/Kconfig.soc b/soc/arm/renesas_smartbond/da1469x/Kconfig.soc
@@ -9,3 +9,18 @@ config SOC_DA14699
 	bool "DA14699"
 
 endchoice
+
+config SOC_DCDC_DA1469X
+	bool
+	help
+	  Enable DA1469x sereis SoC DC/DC converter
+
+config SOC_DCDC_DA1469X_1V8
+	bool
+	help
+	  Enable DA1469x sereis SoC DC/DC converter on 1V8 rail
+
+config SOC_DCDC_DA1469X_1V8P
+	bool
+	help
+	  Enable DA1469x sereis SoC DC/DC converter on 1V8P rail
diff --git a/soc/arm/renesas_smartbond/da1469x/power.c b/soc/arm/renesas_smartbond/da1469x/power.c
@@ -155,6 +155,10 @@ __weak void pm_state_set(enum pm_state state, uint8_t substate_id)
 				SYS_WDOG->WATCHDOG_REG = SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Msk;
 			}
 
+#if defined(CONFIG_SOC_DCDC_DA1469X)
+			z_smartbond_restore_dcdc();
+#endif
+
 			da1469x_pd_acquire(MCU_PD_DOMAIN_SYS);
 
 			if (z_smartbond_is_wakeup_by_jtag()) {

diff --git a/soc/arm/renesas_smartbond/da1469x/soc.c b/soc/arm/renesas_smartbond/da1469x/soc.c
@@ -46,6 +46,18 @@ LOG_MODULE_REGISTER(soc);
 static uint32_t z_renesas_cache_configured;
 #endif
 
+#if defined(CONFIG_PM) && defined(CONFIG_SOC_DCDC_DA1469X)
+struct dcdc_regs {
+	uint32_t v18;
+	uint32_t v18p;
+	uint32_t vdd;
+	uint32_t v14;
+	uint32_t ctrl1;
+};
+
+static struct dcdc_regs dcdc_state;
+#endif
+
 void sys_arch_reboot(int type)
 {
 	ARG_UNUSED(type);
@@ -59,6 +71,68 @@ z_smartbond_vdd_level_set(uint8_t vdd_level)
 	POWER_CTRL_REG_SET(VDD_LEVEL, vdd_level);
 }
 
+#if defined(CONFIG_SOC_DCDC_DA1469X)
+static void configure_dcdc(void)
+{
+#if defined(CONFIG_SOC_DCDC_DA1469X_1V8)
+	DCDC->DCDC_V18_REG |= DCDC_DCDC_V18_REG_DCDC_V18_ENABLE_HV_Msk;
+	DCDC->DCDC_V18_REG &= ~DCDC_DCDC_V18_REG_DCDC_V18_ENABLE_LV_Msk;
+#else
+	DCDC->DCDC_V18_REG &= ~DCDC_DCDC_V18_REG_DCDC_V18_ENABLE_HV_Msk;
+	DCDC->DCDC_V18_REG &= ~DCDC_DCDC_V18_REG_DCDC_V18_ENABLE_LV_Msk;
+#endif
+
+#if defined(CONFIG_SOC_DCDC_DA1469X_1V8P)
+	DCDC->DCDC_V18P_REG |= DCDC_DCDC_V18P_REG_DCDC_V18P_ENABLE_HV_Msk;
+	DCDC->DCDC_V18P_REG &= ~DCDC_DCDC_V18P_REG_DCDC_V18P_ENABLE_LV_Msk;
+#else
+	DCDC->DCDC_V18P_REG &= ~DCDC_DCDC_V18P_REG_DCDC_V18P_ENABLE_HV_Msk;
+	DCDC->DCDC_V18P_REG &= ~DCDC_DCDC_V18P_REG_DCDC_V18P_ENABLE_LV_Msk;
+#endif
+
+	DCDC->DCDC_VDD_REG |= DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_HV_Msk;
+	DCDC->DCDC_VDD_REG |= DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_LV_Msk;
+
+	DCDC->DCDC_V14_REG |= DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_HV_Msk;
+	DCDC->DCDC_V14_REG |= DCDC_DCDC_VDD_REG_DCDC_VDD_ENABLE_LV_Msk;
+
+#if defined(CONFIG_PM)
+	/* Store DCDC registers to quickly restore DCDC state after wakeup */
+	dcdc_state.v18 = DCDC->DCDC_V18_REG;
+	dcdc_state.v18p = DCDC->DCDC_V18P_REG;
+	dcdc_state.vdd = DCDC->DCDC_VDD_REG;
+	dcdc_state.v14 = DCDC->DCDC_V14_REG;
+	dcdc_state.ctrl1 = DCDC->DCDC_CTRL1_REG;
+#endif
+
+	/*
+	 * Enabling DCDC while VBAT is below 2.5 V renders system unstable even
+	 * if VBUS is available. Enable DCDC only if VBAT is above minimal value.
+	 */
+	if (CRG_TOP->ANA_STATUS_REG & CRG_TOP_ANA_STATUS_REG_COMP_VBAT_HIGH_Msk) {
+		DCDC->DCDC_CTRL1_REG |= DCDC_DCDC_CTRL1_REG_DCDC_ENABLE_Msk;
+	}
+}
+
+void z_smartbond_restore_dcdc(void)
+{
+	/*
+	 * Enabling DCDC while VBAT is below 2.5 V renders system unstable even
+	 * if VBUS is available. Enable DCDC only if VBAT is above minimal value.
+	 */
+	if (CRG_TOP->ANA_STATUS_REG & CRG_TOP_ANA_STATUS_REG_COMP_VBAT_HIGH_Msk) {
+#if defined(CONFIG_PM)
+		DCDC->DCDC_V18_REG = dcdc_state.v18;
+		DCDC->DCDC_V18P_REG = dcdc_state.v18p;
+		DCDC->DCDC_VDD_REG = dcdc_state.vdd;
+		DCDC->DCDC_V14_REG = dcdc_state.v14;
+		DCDC->DCDC_CTRL1_REG = dcdc_state.ctrl1;
+#endif
+		DCDC->DCDC_CTRL1_REG |= DCDC_DCDC_CTRL1_REG_DCDC_ENABLE_Msk;
+	}
+}
+#endif
+
 static void z_smartbond_configure_power_rails(void)
 {
 	POWER_CTRL_REG_SET(LDO_3V0_MODE, 3);
@@ -95,6 +169,10 @@ static void z_smartbond_configure_power_rails(void)
 	POWER_CTRL_REG_SET(LDO_CORE_ENABLE, 1);
 
 	POWER_CTRL_REG_SET(V14_LEVEL, V14_LEVEL_1V40);
+
+#if defined(CONFIG_SOC_DCDC_DA1469X)
+	configure_dcdc();
+#endif
 }
 
 #if defined(CONFIG_BOOTLOADER_MCUBOOT)

diff --git a/soc/arm/renesas_smartbond/da1469x/soc.h b/soc/arm/renesas_smartbond/da1469x/soc.h
@@ -17,6 +17,7 @@ int z_smartbond_sleep(void);
 void z_smartbond_wakeup_handler(void);
 void z_smartbond_wakeup(void);
 void z_smartbond_restore_state(void);
+void z_smartbond_restore_dcdc(void);
 
 #define VDD_LEVEL_0V9		0
 #define VDD_LEVEL_1V2		3