feat(ntt): avoid panicking on non prime inputs

src/prime32.rs

@@ -1,6 +1,7 @@
 use crate::{
     bit_rev,
     fastdiv::{Div32, Div64},
+    prime::is_prime64,
     roots::find_primitive_root64,
 };
 use aligned_vec::{avec, ABox};
@@ -632,6 +633,8 @@ impl Plan {
         // as SIMD registers can contain at most 16*u32
         // and the implementation assumes that SIMD registers are full
         if polynomial_size < 32
+            || !polynomial_size.is_power_of_two()
+            || !is_prime64(modulus as u64)
             || find_primitive_root64(Div64::new(modulus as u64), 2 * polynomial_size as u64)
                 .is_none()
         {

src/prime64.rs

@@ -1,4 +1,4 @@
-use crate::{bit_rev, fastdiv::Div64, roots::find_primitive_root64};
+use crate::{bit_rev, fastdiv::Div64, prime::is_prime64, roots::find_primitive_root64};
 use aligned_vec::{avec, ABox};
 
 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
@@ -707,6 +707,8 @@ impl Plan {
         // as SIMD registers can contain at most 8*u64
         // and the implementation assumes that SIMD registers are full
         if polynomial_size < 16
+            || !polynomial_size.is_power_of_two()
+            || !is_prime64(modulus)
             || find_primitive_root64(p_div, 2 * polynomial_size as u64).is_none()
         {
             None
@@ -1869,4 +1871,9 @@ mod x86_tests {
             assert_eq!(val, val_target);
         }
     }
+
+    #[test]
+    fn test_plan_crash_github_11() {
+        assert!(Plan::try_new(2048, 1024).is_none());
+    }
 }