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serge-sans-paille committed Oct 15, 2024
1 parent eb9e0e4 commit fc489c4
Showing 1 changed file with 15 additions and 3 deletions.
18 changes: 15 additions & 3 deletions include/xsimd/types/xsimd_rvv_register.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -95,10 +95,10 @@ namespace xsimd
} \
template <> \
XSIMD_INLINE type bitcast<type>(type x) noexcept { return x; } \
static XSIMD_INLINE byte_type as_bytes(type x) noexcept \
template <class U> \
static XSIMD_INLINE byte_type as_bytes(U x) noexcept \
{ \
const auto words = XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, s, m, vmul)(x); \
return XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, 8, m, vmul)(words); \
return XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, 8, m, vmul)(x); \
} \
};

Expand Down Expand Up @@ -133,6 +133,18 @@ namespace xsimd
{
return __riscv_vreinterpret_i8m8(x);
}
template <>
XSIMD_INLINE rvv_type_info<int8_t, rvv_width_m1 * 8>::byte_type
rvv_type_info<int8_t, rvv_width_m1 * 8>::as_bytes<__rvv_int8m8_t>(__rvv_int8m8_t x) noexcept
{
return __riscv_vreinterpret_u8m8(x);
}
template <>
XSIMD_INLINE rvv_type_info<uint32_t, rvv_width_m1 * 1>::byte_type
rvv_type_info<uint32_t, rvv_width_m1 * 1>::as_bytes<__rvv_uint32m1_t>(__rvv_uint32m1_t x) noexcept
{
return __riscv_vreinterpret_u8m1(x);
}

// rvv_blob is storage-type abstraction for a vector register.
template <class T, size_t Width>
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