[WIP] Fix clang-17 miscompilation of __riscv_vreinterpret_u8m8

xtensor-stack · Oct 15, 2024 · ac99806 · ac99806
1 parent e4e871c
commit ac99806
Showing 1 changed file with 8 additions and 0 deletions.
diff --git a/include/xsimd/types/xsimd_rvv_register.hpp b/include/xsimd/types/xsimd_rvv_register.hpp
@@ -125,6 +125,14 @@ namespace xsimd
 #undef XSIMD_RVV_MAKE_TYPES
 #undef XSIMD_RVV_MAKE_TYPE
 
+    template<>
+    template<>
+    static XSIMD_INLINE rvv_type_info<uint8_t, rvv_width_m1 * 8>::type
+    rvv_type_info<uint8_t, rvv_width_m1 * 8>::bitcast<int8_t>(int8_t x) noexcept
+    {
+      return __riscv_vreinterpret_u8m8(x);
+    }
+
             // rvv_blob is storage-type abstraction for a vector register.
             template <class T, size_t Width>
             struct rvv_blob : public rvv_type_info<T, Width>