Merge pull request #979 from rivosinc/upstream-rvv

Add RISC-V Vector support.

.github/toolchains/clang-riscv64-linux-gnu.cmake

@@ -0,0 +1,4 @@
+set(CMAKE_SYSTEM_PROCESSOR riscv64)
+set(triple riscv64-linux-gnu)
+
+include(${CMAKE_CURRENT_LIST_DIR}/clang.cmake)

.github/toolchains/gcc-riscv64-linux-gnu.cmake

@@ -0,0 +1,4 @@
+set(CMAKE_SYSTEM_PROCESSOR riscv64)
+set(triple riscv64-linux-gnu)
+
+include(${CMAKE_CURRENT_LIST_DIR}/gcc.cmake)

.github/workflows/cross-rvv.yml

@@ -0,0 +1,62 @@
+name: RISC-V RVV cross-compilation build
+on: [push, pull_request]
+concurrency:
+  group: ${{ github.workflow }}-${{ github.job }}-${{ github.ref }}
+  cancel-in-progress: true
+env:
+  LLVM_VERSION: "17"
+  GCC_VERSION: "12"
+jobs:
+  build:
+    runs-on: ubuntu-22.04
+    name: 'RISC-V RVV${{ matrix.vector_bits }}'
+    strategy:
+      matrix:
+        vector_bits:
+          - 128
+          - 256
+          - 512
+    steps:
+    - name: Setup GCC
+      run: |
+        sudo apt-get -y -qq update
+        sudo apt-get -y -qq --no-install-suggests --no-install-recommends install gcc-${GCC_VERSION}-riscv64-linux-gnu g++-${GCC_VERSION}-riscv64-linux-gnu
+        sudo update-alternatives --install /usr/bin/riscv64-linux-gnu-gcc riscv64-linux-gnu-gcc /usr/bin/riscv64-linux-gnu-gcc-${GCC_VERSION} 20
+        sudo update-alternatives --install /usr/bin/riscv64-linux-gnu-g++ riscv64-linux-gnu-g++ /usr/bin/riscv64-linux-gnu-g++-${GCC_VERSION} 20
+    - name: Setup LLVM
+      run: |
+        # Install latest LLVM stable
+        curl -o llvm.sh https://apt.llvm.org/llvm.sh
+        chmod u+x llvm.sh
+        sudo ./llvm.sh ${LLVM_VERSION}
+        sudo ln -srf $(which clang-${LLVM_VERSION}) /usr/bin/clang
+        sudo ln -srf $(which clang++-${LLVM_VERSION}) /usr/bin/clang++
+        rm llvm.sh
+    - name: Setup QEMU
+      uses: docker/[email protected]
+      with:
+        platforms: riscv64
+    - name: Setup Ninja
+      run: |
+        sudo apt-get -y -qq install ninja-build
+    - name: Checkout xsimd
+      uses: actions/checkout@v3
+    - name: Setup
+      run: >
+        cmake -S . -B _build
+        -GNinja
+        -DBUILD_TESTS=ON
+        -DDOWNLOAD_DOCTEST=ON
+        -DCMAKE_BUILD_TYPE=Release
+        -DTARGET_ARCH=generic
+        -DCMAKE_C_FLAGS="-march=rv64gcv_zvl${{ matrix.vector_bits }}b_zba_zbb_zbs -mrvv-vector-bits=zvl"
+        -DCMAKE_CXX_FLAGS="-march=rv64gcv_zvl${{ matrix.vector_bits }}b_zba_zbb_zbs -mrvv-vector-bits=zvl"
+        -DCMAKE_TOOLCHAIN_FILE=${{ github.workspace }}/.github/toolchains/clang-riscv64-linux-gnu.cmake
+    - name: Build
+      run: cmake --build _build
+    - name: Testing xsimd
+      run: >
+        QEMU_CPU="rv64,zba=true,zbb=true,zbs=true,v=true,vlen=${{ matrix.vector_bits }},elen=64,vext_spec=v1.0"
+        QEMU_LD_PREFIX="/usr/riscv64-linux-gnu"
+        ./test/test_xsimd
+      working-directory: ${{ github.workspace }}/_build

CMakeLists.txt

@@ -42,6 +42,7 @@ ${XSIMD_INCLUDE_DIR}/xsimd/arch/xsimd_generic.hpp
 ${XSIMD_INCLUDE_DIR}/xsimd/arch/xsimd_isa.hpp
 ${XSIMD_INCLUDE_DIR}/xsimd/arch/xsimd_neon.hpp
 ${XSIMD_INCLUDE_DIR}/xsimd/arch/xsimd_neon64.hpp
+${XSIMD_INCLUDE_DIR}/xsimd/arch/xsimd_rvv.hpp
 ${XSIMD_INCLUDE_DIR}/xsimd/arch/xsimd_scalar.hpp
 ${XSIMD_INCLUDE_DIR}/xsimd/arch/xsimd_sse2.hpp
 ${XSIMD_INCLUDE_DIR}/xsimd/arch/xsimd_sse3.hpp
@@ -69,6 +70,7 @@ ${XSIMD_INCLUDE_DIR}/xsimd/types/xsimd_fma3_sse_register.hpp
 ${XSIMD_INCLUDE_DIR}/xsimd/types/xsimd_fma4_register.hpp
 ${XSIMD_INCLUDE_DIR}/xsimd/types/xsimd_generic_arch.hpp
 ${XSIMD_INCLUDE_DIR}/xsimd/types/xsimd_register.hpp
+${XSIMD_INCLUDE_DIR}/xsimd/types/xsimd_rvv_register.hpp
 ${XSIMD_INCLUDE_DIR}/xsimd/types/xsimd_sse2_register.hpp
 ${XSIMD_INCLUDE_DIR}/xsimd/types/xsimd_sse3_register.hpp
 ${XSIMD_INCLUDE_DIR}/xsimd/types/xsimd_sse4_1_register.hpp

docs/Doxyfile

@@ -21,6 +21,7 @@ INPUT             = ../include/xsimd/types/xsimd_api.hpp \
                     ../include/xsimd/types/xsimd_fma4_register.hpp \
                     ../include/xsimd/types/xsimd_neon64_register.hpp \
                     ../include/xsimd/types/xsimd_neon_register.hpp \
+                    ../include/xsimd/types/xsimd_rvv_register.hpp \
                     ../include/xsimd/types/xsimd_sse2_register.hpp \
                     ../include/xsimd/types/xsimd_sse3_register.hpp \
                     ../include/xsimd/types/xsimd_sse4_1_register.hpp \

include/xsimd/arch/xsimd_isa.hpp

@@ -80,6 +80,10 @@
 #include "./xsimd_sve.hpp"
 #endif
 
+#if XSIMD_WITH_RVV
+#include "./xsimd_rvv.hpp"
+#endif
+
 #if XSIMD_WITH_WASM
 #include "./xsimd_wasm.hpp"
 #endif

include/xsimd/config/xsimd_arch.hpp

@@ -192,14 +192,17 @@ namespace xsimd
     };
     using all_x86_architectures = arch_list<avx512bw, avx512dq, avx512cd, avx512f, fma3<avx2>, avx2, fma3<avx>, avx, fma4, fma3<sse4_2>, sse4_2, sse4_1, /*sse4a,*/ ssse3, sse3, sse2>;
     using all_sve_architectures = arch_list<detail::sve<512>, detail::sve<256>, detail::sve<128>>;
+    using all_rvv_architectures = arch_list<detail::rvv<512>, detail::rvv<256>, detail::rvv<128>>;
     using all_arm_architectures = typename detail::join<all_sve_architectures, arch_list<neon64, neon>>::type;
+    using all_riscv_architectures = all_rvv_architectures;
     using all_wasm_architectures = arch_list<wasm>;
-    using all_architectures = typename detail::join<all_arm_architectures, all_x86_architectures, all_wasm_architectures>::type;
+    using all_architectures = typename detail::join<all_arm_architectures, all_x86_architectures, all_riscv_architectures, all_wasm_architectures>::type;
 
     using supported_architectures = typename detail::supported<all_architectures>::type;
 
     using x86_arch = typename detail::supported<all_x86_architectures>::type::best;
     using arm_arch = typename detail::supported<all_arm_architectures>::type::best;
+    using riscv_arch = typename detail::supported<all_riscv_architectures>::type::best;
     using best_arch = typename supported_architectures::best;
 
 #ifdef XSIMD_DEFAULT_ARCH

include/xsimd/config/xsimd_config.hpp

@@ -285,6 +285,19 @@
 #define XSIMD_SVE_BITS 0
 #endif
 
+/**
+ * @ingroup xsimd_config_macro
+ *
+ * Set to 1 if RVV is available and bit width is pre-set at compile-time, to 0 otherwise.
+ */
+#if defined(__riscv_vector) && defined(__riscv_v_fixed_vlen) && __riscv_v_fixed_vlen > 0
+#define XSIMD_WITH_RVV 1
+#define XSIMD_RVV_BITS __riscv_v_fixed_vlen
+#else
+#define XSIMD_WITH_RVV 0
+#define XSIMD_RVV_BITS 0
+#endif
+
 /**
  * @ingroup xsimd_config_macro
  *
@@ -354,7 +367,7 @@
 
 #endif
 
-#if !XSIMD_WITH_SSE2 && !XSIMD_WITH_SSE3 && !XSIMD_WITH_SSSE3 && !XSIMD_WITH_SSE4_1 && !XSIMD_WITH_SSE4_2 && !XSIMD_WITH_AVX && !XSIMD_WITH_AVX2 && !XSIMD_WITH_FMA3_SSE && !XSIMD_WITH_FMA4 && !XSIMD_WITH_FMA3_AVX && !XSIMD_WITH_FMA3_AVX2 && !XSIMD_WITH_AVX512F && !XSIMD_WITH_AVX512CD && !XSIMD_WITH_AVX512DQ && !XSIMD_WITH_AVX512BW && !XSIMD_WITH_NEON && !XSIMD_WITH_NEON64 && !XSIMD_WITH_SVE && !XSIMD_WITH_WASM
+#if !XSIMD_WITH_SSE2 && !XSIMD_WITH_SSE3 && !XSIMD_WITH_SSSE3 && !XSIMD_WITH_SSE4_1 && !XSIMD_WITH_SSE4_2 && !XSIMD_WITH_AVX && !XSIMD_WITH_AVX2 && !XSIMD_WITH_FMA3_SSE && !XSIMD_WITH_FMA4 && !XSIMD_WITH_FMA3_AVX && !XSIMD_WITH_FMA3_AVX2 && !XSIMD_WITH_AVX512F && !XSIMD_WITH_AVX512CD && !XSIMD_WITH_AVX512DQ && !XSIMD_WITH_AVX512BW && !XSIMD_WITH_NEON && !XSIMD_WITH_NEON64 && !XSIMD_WITH_SVE && !XSIMD_WITH_RVV && !XSIMD_WITH_WASM
 #endif
 
 #endif

include/xsimd/config/xsimd_cpuid.hpp

@@ -15,7 +15,7 @@
 #include <algorithm>
 #include <cstring>
 
-#if defined(__linux__) && (defined(__ARM_NEON) || defined(_M_ARM))
+#if defined(__linux__) && (defined(__ARM_NEON) || defined(_M_ARM) || defined(__riscv_vector))
 #include <asm/hwcap.h>
 #include <sys/auxv.h>
 #endif
@@ -53,6 +53,7 @@ namespace xsimd
             unsigned neon : 1;
             unsigned neon64 : 1;
             unsigned sve : 1;
+            unsigned rvv : 1;
 
             // version number of the best arch available
             unsigned best;
@@ -85,6 +86,18 @@ namespace xsimd
 #endif
                 best = sve::version() * sve;
 
+#elif defined(__riscv_vector) && defined(__riscv_v_fixed_vlen) && __riscv_v_fixed_vlen > 0
+
+#if defined(__linux__) && (!defined(__ANDROID_API__) || __ANDROID_API__ >= 18)
+#ifndef HWCAP_V
+#define HWCAP_V (1 << ('V' - 'A'))
+#endif
+                rvv = bool(getauxval(AT_HWCAP) & HWCAP_V);
+#else
+                rvv = 0;
+#endif
+
+                best = ::xsimd::rvv::version() * rvv;
 #elif defined(__x86_64__) || defined(__i386__) || defined(_M_AMD64) || defined(_M_IX86)
                 auto get_cpuid = [](int reg[4], int func_id) noexcept
                 {

include/xsimd/types/xsimd_all_registers.hpp

@@ -31,4 +31,6 @@
 
 #include "xsimd_sve_register.hpp"
 
+#include "xsimd_rvv_register.hpp"
+
 #include "xsimd_wasm_register.hpp"

include/xsimd/types/xsimd_generic_arch.hpp

@@ -41,7 +41,7 @@ namespace xsimd
         static constexpr char const* name() noexcept { return "generic"; }
 
     protected:
-        static constexpr unsigned version(unsigned major, unsigned minor, unsigned patch) noexcept { return major * 10000u + minor * 100u + patch; }
+        static constexpr unsigned version(unsigned major, unsigned minor, unsigned patch, unsigned multiplier = 100u) noexcept { return major * multiplier * multiplier + minor * multiplier + patch; }
     };
 }