[WIP] Fix clang-17 miscompilation of __riscv_vreinterpret_u8m8

xtensor-stack · Oct 15, 2024 · 0b5ba50 · 0b5ba50
1 parent e4e871c
commit 0b5ba50
Showing 1 changed file with 4 additions and 0 deletions.
diff --git a/include/xsimd/types/xsimd_rvv_register.hpp b/include/xsimd/types/xsimd_rvv_register.hpp
@@ -95,6 +95,10 @@ namespace xsimd
         }                                                                                 \
         template <>                                                                       \
         XSIMD_INLINE type bitcast<type>(type x) noexcept { return x; }                    \
+        template <>                                                                       \
+        XSIMD_INLINE type bitcast<byte_type>(byte_type x) noexcept {                      \
+          return XSIMD_RVV_JOINT5(__riscv_vreinterpret_, t, s, m, vmul)(words);           \
+        }                                                                                 \
         static XSIMD_INLINE byte_type as_bytes(type x) noexcept                           \
         {                                                                                 \
             const auto words = XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, s, m, vmul)(x); \