Updated main branch to alpha v1.0.0

.github/workflows/demo_build.yml

@@ -0,0 +1,34 @@
+# Copyright (c) 2024, Victor Chavez
+# SPDX-License-Identifier: GPL-3.0-or-later
+
+name: Build Demo
+
+on:
+  push:
+  pull_request:
+
+jobs:
+
+  build:
+    runs-on: ubuntu-22.04
+    container: ghcr.io/zephyrproject-rtos/ci:v0.26.2
+    env:
+      CMAKE_PREFIX_PATH: /opt/toolchains
+      ZEPHYR_VERSION: v3.6-branch
+      # Board to use with renode
+      BOARD: nrf52833dk_nrf52833
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v4
+        with:
+          submodules: true
+      - name: Initialize
+        run: |
+          cd /tmp/
+          west init
+          west update -o=--depth=1 -n
+
+      - name: Build PoC
+        working-directory: /tmp/
+        run: |
+          west build $GITHUB_WORKSPACE/samples/demo -b $BOARD --build-dir $GITHUB_WORKSPACE/build

.github/workflows/samples_build.yml

@@ -0,0 +1,34 @@
+# Copyright (c) 2024, Victor Chavez
+# SPDX-License-Identifier: GPL-3.0-or-later
+
+name: Build Samples
+
+on:
+  push:
+  pull_request:
+
+jobs:
+
+  read_pd:
+    runs-on: ubuntu-22.04
+    container: ghcr.io/zephyrproject-rtos/ci:v0.26.2
+    env:
+      CMAKE_PREFIX_PATH: /opt/toolchains
+      ZEPHYR_VERSION: v3.6-branch
+      # Board to use with renode
+      BOARD: nrf52833dk_nrf52833
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v4
+        with:
+          submodules: true
+      - name: Initialize
+        run: |
+          cd /tmp/
+          west init
+          west update -o=--depth=1 -n
+
+      - name: Build PoC
+        working-directory: /tmp/
+        run: |
+          west build $GITHUB_WORKSPACE/samples/read_pd -b $BOARD --build-dir $GITHUB_WORKSPACE/build

.gitignore

@@ -0,0 +1,36 @@
+samples/*/build*
+*.vscode
+# Prerequisites
+*.d
+
+# Compiled Object files
+*.slo
+*.lo
+*.o
+*.obj
+
+# Precompiled Headers
+*.gch
+*.pch
+
+# Compiled Dynamic libraries
+*.so
+*.dylib
+*.dll
+
+# Fortran module files
+*.mod
+*.smod
+
+# Compiled Static libraries
+*.lai
+*.la
+*.a
+*.lib
+
+# Executables
+*.exe
+*.out
+*.app
+
+*/build/*

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "i-link"]
+	path = i-link
+	url = https://github.com/vChavezB/i-link/

CMakeLists.txt

@@ -0,0 +1,42 @@
+# Copyright (c) 2024 Victor Chavez
+# SPDX-License-Identifier: GPL-3.0-or-later
+
+if(CONFIG_IOLINK)
+    set(lib_name iolink_master)
+    set(OSAL_DIR ${CMAKE_CURRENT_SOURCE_DIR}/osal)
+    set(IOL_OSAL_DIR ${CMAKE_CURRENT_SOURCE_DIR}/iol_osal)
+    set(STACK_DIR ${CMAKE_CURRENT_SOURCE_DIR}/i-link)
+    set(STACK_SRC ${STACK_DIR}/src)
+    zephyr_library_named(${lib_name})
+    # todo separate private and public 
+    zephyr_include_directories( ${STACK_DIR}/include
+                                ${STACK_DIR}/include/src
+                                ${STACK_DIR}/src
+                                ${STACK_DIR}/iol_osal/include
+                                ${CMAKE_CURRENT_SOURCE_DIR}/src/osal
+                                ${CMAKE_CURRENT_SOURCE_DIR}/src
+                                include
+        )
+
+    zephyr_library_sources(${STACK_SRC}/iolink_al.c
+                            ${STACK_SRC}/iolink_cm.c
+                            ${STACK_SRC}/iolink_dl.c
+                            ${STACK_SRC}/iolink_ds.c
+                            ${STACK_SRC}/iolink_main.c
+                            ${STACK_SRC}/iolink_max14819_pl.c
+                            ${STACK_SRC}/iolink_ode.c
+                            ${STACK_SRC}/iolink_pde.c
+                            ${STACK_SRC}/iolink_pl.c
+                            ${STACK_SRC}/iolink_sm.c
+                            src/osal/osal.c
+                            src/osal/osal_log.c
+                            src/iolm.c
+                            src/utils.c
+                            src/transciever.c)
+
+    #zephyr_library_sources_ifdef(CONFIG_XX xx)
+    #target_compile_definitions(${lib_name} PUBLIC MY_DEF="123")
+    target_include_directories(${lib_name} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/dts/bindings/iolm)
+    target_compile_options(${lib_name} PRIVATE -Wfatal-errors)
+endif()
+

README.md

@@ -4,8 +4,44 @@ This repository integrates a [forked](https://github.com/vChavezB/i-link/tree/ze
 
 ## Supported PHYS
 
-The RT-Labs stack only supports the MAX14189 PHY. This requires only from the Zephyr board side an SPI interface and an IRQ pin.
+The RT-Labs stack only supports the MAX14189 PHY. This requires a Zephyr board that has an SPI interface and GPIOs for the Chip select and IRQ.
+
+## License
+
+The IO-Link stack (i.e., backend) is provided by RT-Labs as GPLv3.0. Hence This Zephyr port
+is also licensed as GPLv3.0.
+
+## Tested boards
+
+- ESP32 Devkit C
+- NRF52833 DK
+
+Zephyr version v3.6.99 commit `34c84eccec0508b16f5001b20fa369f387d856df`
+
+## Testing
+
+A sample to test the current API for this project is located in `samples/read_pd`.
 
 ## Current Status
 
-This repository is under development and will not provide a stable API until the first release version.
+This project is in alpha version and will not provide a stable API/Documentation until the first release.
+
+Currently building API to use easily the IOLM Stack.
+
+## Issues
+
+- Legacy devices (V.1.0) do not go to operate. Some tests have been done and it seems
+that the RT-Labs stack cannot process events for legacy devices. The device goes to operate
+but the System Managemen (SM) and SMI Configuration Management (CM) do not report back this change.
+This happens as it seems that the OD Handler for the event state machine gets stuck.
+
+
+### TODOS
+
+- Test Port Cfg with Validation (VID,DID, V10,V11)
+- Wrapper for direct access to SMI Requests
+- Test SMI Device Read/Write
+
+
+
+

dts/bindings/iolm/iol,maxim14819.yaml

@@ -0,0 +1,69 @@
+# Copyright (c) 2024 Victor Chavez
+# SPDX-License-Identifier: GPL-3.0-or-later
+
+description: >
+  Binding for the MAXIM14819 IOLM Transciever
+
+compatible: "iolm,maxim14819"
+
+include: [ spi-device.yaml ]
+
+properties:
+  irq-gpios:
+    type: phandle-array
+    required: true
+    description: GPIO pin used for irq
+
+
+  chip-address:
+    description: SPI address of the transceiver
+    type: int
+    required: true
+
+  IntE:
+    description: Initial value of the InterruptEn register
+    type: int
+
+  CQCtrlA:
+    description: Initial value of the CQCtrlA register
+    type: int
+
+  CQCtrlB:
+    description: Initial value of the CQCtrlB register
+    type: int
+
+  LEDCtrl:
+    description: Initial value of the LEDCtrl register
+    type: int
+
+  CQCfgA:
+    description: Initial value of the CQCfgA register
+    type: int
+
+  CQCfgB:
+    description: Initial value of the CQCfgB register
+    type: int
+
+  LPCnfgA:
+    description: Initial value of the LPCnfgA register
+    type: int
+
+  LPCnfgB:
+    description: Initial value of the LPCnfgB register
+    type: int
+
+  IOStCfgA:
+    description: Initial value of the IOStCfgA register
+    type: int
+
+  IOStCfgB:
+    description: Initial value of the IOStCfgB register
+    type: int
+
+  DrvCurrLim:
+    description: Initial value of the DrvCurrLim register
+    type: int
+
+  Clock:
+    description: Initial value of the Clock register
+    type: int

dts/bindings/iolm/maxim14819.h

@@ -0,0 +1,48 @@
+/*  Copyright (c) 2024 Victor Chavez
+    SPDX-License-Identifier: GPL-3.0-or-later
+*/
+#define CQCFG_CQFILTEREN    BIT(0)
+#define CQCFG_DRVDIS        BIT(1)
+#define CQCFG_PUSHPUL       BIT(2)
+#define CQCFG_NPN           BIT(3)
+#define CQCFG_SINKSEL(x)    (((x) & 0x03) << 4)
+#define CQCFG_SINKSEL_MASK  CQCFG_SINKSEL (0x3)
+#define CQCFG_SOURCESINK    BIT(6)
+#define CQCFG_IEC3TH        BIT(7)
+
+#define CLOCK_XTALEN        BIT (0)
+#define CLOCK_EXTCLKEN      BIT (1)
+#define CLOCK_CLKDIV(x)     (((x) & 0x03) << 2)
+#define CLOCK_CLKDIV_MASK   CLOCK_CLKDIV (0x03)
+#define CLOCK_CLKOEN        BIT (4)
+#define CLOCK_EXTCLKMIS     BIT (5)
+#define CLOCK_TXTXENDIS     BIT (6)
+#define CLOCK_VCCWARNEN     BIT (7)
+
+#define IOSTCFG_DICSINK     BIT (0)
+#define IOSTCFG_DICSOURCE   BIT (1)
+#define IOSTCFG_DIEC3TH     BIT (2)
+#define IOSTCFG_DIFILTEREN  BIT (3)
+#define IOSTCFG_TX          BIT (4)
+#define IOSTCFG_TXEN        BIT (5)
+#define IOSTCFG_CQLEVEL     BIT (6)
+#define IOSTCFG_DILEVEL     BIT (7)
+
+#define LPCNFG_LPEN         BIT (0)
+#define LPCNFG_LPCLIMDIS    BIT (1)
+#define LPCNFG_LPCL2X       BIT (2)
+#define LPCNFG_LPBL(x)      (((x) & 0x03) << 3)
+#define LPCNFG_LPBL_MASK    LPCNFG_BLA (0x03)
+#define LPCNFG_LPDYNBL      BIT (5)
+#define LPCNFG_LPRT(x)      (((x) & 0x03) << 6)
+#define LPCNFG_LPRT_MASK    LPCNFG_BLA (0x03)
+
+#define CURR_100MA 0x00
+#define CURR_200MA 0x01
+#define CURR_300MA 0x02
+#define CURR_500MA 0x03
+#define DRVRCURRLIM_CLDIS BIT(5)
+
+#define CURR_OFF 0x06
+
+#define CL_CONF(x)  ((x) << CURR_OFF)

include/iolm/iolm.h

@@ -0,0 +1,73 @@
+/*  Copyright (c) 2024 Victor Chavez
+    SPDX-License-Identifier: GPL-3.0-or-later
+*/
+#pragma once
+
+#include <stdint.h>
+#include <stddef.h>
+#include <iolink.h>
+#include <iolink_types.h>
+
+struct iolm_port_cfg {
+    uint16_t vid;        // Required if validation = IOLINK_VALIDATION_CHECK_V11_RESTORE or IOLINK_VALIDATION_CHECK_V11_BAK_RESTORE
+    uint32_t did;    // Required if validation = IOLINK_VALIDATION_CHECK_V11_RESTORE or IOLINK_VALIDATION_CHECK_V11_BAK_RESTORE
+    uint32_t cycle_time_us; // Desired cycle time in microseconds, initialize to 0 if you want to set As fast as Possible
+    iolink_portmode_t portmode;
+    iolink_validation_check_t validation;
+};
+
+
+enum iolm_port_evt{
+    IOLM_PORT_PD= 0,    // New PD cycle data available
+    IOLM_PORT_STATUS,   // Port status changed
+    IOLM_PORT_DEV_EVT     // Device event
+};
+
+struct iolm_pd_data {
+    const uint8_t * data;
+    size_t len;
+};
+
+/**
+ * @brief IO-Link Device event entry
+ * 
+ */
+struct iolm_evt_entry {
+    iolink_event_mode_t mode;
+    iolink_event_type_t type;
+    uint16_t event_code;
+};
+
+/**
+ * @brief IO-Link Master device event
+ * 
+ */
+struct iolm_dev_evt {
+    struct iolm_evt_entry * entry;
+    size_t len;
+};
+
+/**
+ * @brief  IO-Link Master port event callback
+ * 
+ */
+typedef void (*iolm_port_evt_cb)(uint8_t port, enum iolm_port_evt evt, void *data, void *arg);
+
+/**
+ * @brief Initialize the IO-Link Master
+ * @param init_cfg Initial configuration for the IO-Link ports. If NULL is passed
+ *                  all the ports will be set to IOLINK_PORTMODE_IOL_AUTO and the cycle time as fast as possible
+ * @return 0 on success
+ *          -ENODEV When a driver fails to initialize or Master struct failed to initialize
+ *          -EIO When port configuration failed
+ */
+int iolm_init(const struct iolm_port_cfg * init_cfg);
+
+/**
+ * @brief  Set the IO-Link Master port event callback
+ * 
+ * @param cb   Callback function
+ * @param arg  Argument to be passed to the callback
+ */
+void iolm_set_port_evt_cb(iolm_port_evt_cb cb, void * arg);
+