- Removed dynamic memory allocation

- Added sample/demo
- Added dts binding for transciever

CMakeLists.txt

@@ -28,14 +28,13 @@ if(CONFIG_IOLINK)
                             ${STACK_SRC}/iolink_pde.c
                             ${STACK_SRC}/iolink_pl.c
                             ${STACK_SRC}/iolink_sm.c
-                            src/iol_osal/osal_spi.c
-                            src/iol_osal/osal_irq.c
                             src/osal/osal.c
-                            src/osal/osal_log.c)
+                            src/osal/osal_log.c
+                            src/transciever.c)
 
     #zephyr_library_sources_ifdef(CONFIG_XX xx)
     #target_compile_definitions(${lib_name} PUBLIC MY_DEF="123")
-    #target_include_directories(${lib_name} PRIVATE lib/etl/include)
+    target_include_directories(${lib_name} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/dts/bindingS/iolm)
     target_compile_options(${lib_name} PRIVATE -Wfatal-errors)
 endif()
 

README.md

@@ -4,26 +4,41 @@ This repository integrates a [forked](https://github.com/vChavezB/i-link/tree/ze
 
 ## Supported PHYS
 
-The RT-Labs stack only supports the MAX14189 PHY. This requires only from the Zephyr board side an SPI interface and an IRQ pin.
+The RT-Labs stack only supports the MAX14189 PHY. This requires a Zephyr board that has an SPI interface and GPIOs for the Chip select and IRQ.
 
 ## License
 
 The IO-Link stack (i.e., backend) is provided by RT-Labs as GPLv3.0. Hence This Zephyr port
 is also licensed as GPLv3.0.
 
+## Tested boards
+
+- ESP32 Devkit C
+- NRF52833 DK
+
+Zephyr version v3.6.99 commit `34c84eccec0508b16f5001b20fa369f387d856df`
+
+## Testing
+
+Build and flash the sample located in `samples/demo` and follow the Readme.md
 
 ## Current Status
 
-This repository is under development and will not provide a stable API/Documentation until the first release version.
+This project is in pre-alpha version and will not provide a stable API/Documentation until the first release.
+
+## Issues
+
+- Legacy devices (V.1.0) do not go to operate. Some tests have been done and it seems
+that the RT-Labs stack cannot process events for legacy devices. The device goes to operate
+but the System Managemen (SM) and SMI Configuration Management (CM) do not report back this change.
+This happens as it seems that the OD Handler for the event state machine gets stuck.
+
 
 ### TODOS
 
-- Device Tree bindings for Drivers
 - Friendly API to initialize stack 
-- Test with different boards
-- Stability
-- Samples
 - Documentation (Usage, Caveats)
 
 
 
+

dts/bindings/iolm/iol,maxim14819.yaml

@@ -0,0 +1,69 @@
+# Copyright (c) 2024 Victor Chavez
+# SPDX-License-Identifier: GPL-3.0-or-later
+
+description: >
+  Binding for the MAXIM14819 IOLM Transciever
+
+compatible: "iolm,maxim14819"
+
+include: [ spi-device.yaml ]
+
+properties:
+  irq-gpios:
+    type: phandle-array
+    required: true
+    description: GPIO pin used for irq
+
+
+  chip-address:
+    description: SPI address of the transceiver
+    type: int
+    required: true
+
+  IntE:
+    description: Initial value of the InterruptEn register
+    type: int
+
+  CQCtrlA:
+    description: Initial value of the CQCtrlA register
+    type: int
+
+  CQCtrlB:
+    description: Initial value of the CQCtrlB register
+    type: int
+
+  LEDCtrl:
+    description: Initial value of the LEDCtrl register
+    type: int
+
+  CQCfgA:
+    description: Initial value of the CQCfgA register
+    type: int
+
+  CQCfgB:
+    description: Initial value of the CQCfgB register
+    type: int
+
+  LPCnfgA:
+    description: Initial value of the LPCnfgA register
+    type: int
+
+  LPCnfgB:
+    description: Initial value of the LPCnfgB register
+    type: int
+
+  IOStCfgA:
+    description: Initial value of the IOStCfgA register
+    type: int
+
+  IOStCfgB:
+    description: Initial value of the IOStCfgB register
+    type: int
+
+  DrvCurrLim:
+    description: Initial value of the DrvCurrLim register
+    type: int
+
+  Clock:
+    description: Initial value of the Clock register
+    type: int

dts/bindings/iolm/maxim14819.h

@@ -0,0 +1,48 @@
+/*  Copyright (c) 2024 Victor Chavez
+    SPDX-License-Identifier: GPL-3.0-or-later
+*/
+#define CQCFG_CQFILTEREN    BIT(0)
+#define CQCFG_DRVDIS        BIT(1)
+#define CQCFG_PUSHPUL       BIT(2)
+#define CQCFG_NPN           BIT(3)
+#define CQCFG_SINKSEL(x)    (((x) & 0x03) << 4)
+#define CQCFG_SINKSEL_MASK  CQCFG_SINKSEL (0x3)
+#define CQCFG_SOURCESINK    BIT(6)
+#define CQCFG_IEC3TH        BIT(7)
+
+#define CLOCK_XTALEN        BIT (0)
+#define CLOCK_EXTCLKEN      BIT (1)
+#define CLOCK_CLKDIV(x)     (((x) & 0x03) << 2)
+#define CLOCK_CLKDIV_MASK   CLOCK_CLKDIV (0x03)
+#define CLOCK_CLKOEN        BIT (4)
+#define CLOCK_EXTCLKMIS     BIT (5)
+#define CLOCK_TXTXENDIS     BIT (6)
+#define CLOCK_VCCWARNEN     BIT (7)
+
+#define IOSTCFG_DICSINK     BIT (0)
+#define IOSTCFG_DICSOURCE   BIT (1)
+#define IOSTCFG_DIEC3TH     BIT (2)
+#define IOSTCFG_DIFILTEREN  BIT (3)
+#define IOSTCFG_TX          BIT (4)
+#define IOSTCFG_TXEN        BIT (5)
+#define IOSTCFG_CQLEVEL     BIT (6)
+#define IOSTCFG_DILEVEL     BIT (7)
+
+#define LPCNFG_LPEN         BIT (0)
+#define LPCNFG_LPCLIMDIS    BIT (1)
+#define LPCNFG_LPCL2X       BIT (2)
+#define LPCNFG_LPBL(x)      (((x) & 0x03) << 3)
+#define LPCNFG_LPBL_MASK    LPCNFG_BLA (0x03)
+#define LPCNFG_LPDYNBL      BIT (5)
+#define LPCNFG_LPRT(x)      (((x) & 0x03) << 6)
+#define LPCNFG_LPRT_MASK    LPCNFG_BLA (0x03)
+
+#define CURR_100MA 0x00
+#define CURR_200MA 0x01
+#define CURR_300MA 0x02
+#define CURR_500MA 0x03
+#define DRVRCURRLIM_CLDIS BIT(5)
+
+#define CURR_OFF 0x06
+
+#define CL_CONF(x)  ((x) << CURR_OFF)

include/iolm/transciever.h

@@ -0,0 +1,17 @@
+/*  Copyright (c) 2024 Victor Chavez
+    SPDX-License-Identifier: GPL-3.0-or-later
+*/
+#pragma once
+#include <iolink_pl_hw_drv.h>
+#include <stdint.h>
+
+#define TRANSCIEVER_MAX_PORTS 2
+
+/**
+ * @brief Get the Maxim14819 Driver object initialized in src/transciever.c
+ * 
+ * @param port The IO-Link port number associated to the maxim driver.
+ *              The value should be 0 to CONFIG_IOLINK_NUM_PORTS-1
+ * @return driver object if found, NULL otherwise
+ */
+iolink_hw_drv_t * get_drv(uint8_t port);

samples/ifm_sample_app/CMakeLists.txt → samples/demo/CMakeLists.txt

@@ -5,9 +5,9 @@ cmake_minimum_required(VERSION 3.20.0)
 set(IOLINK_MODULE ${CMAKE_CURRENT_SOURCE_DIR}/../..)
 set(ZEPHYR_EXTRA_MODULES ${IOLINK_MODULE})
 find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(ifm_sample_app)
+project(iolm_demo)
 
 target_sources(app PRIVATE src/iolink_smi.c
                             src/iolink_handler.c
-                            src/iol_master_sample_app.c
+                            src/demo.c
 )

samples/demo/README.md

@@ -0,0 +1,55 @@
+# Zephyr IO-Link Master Demo
+
+A sample application running the Zephyr IO-Link Master module with the i-link rt-lab stack.
+
+## Tested Boards
+
+- NRF52833DK
+- ESP32
+
+## Build and Flash
+
+```
+git clone --recursive https://github.com/vChavezB/zephyr-iolm/
+cd YOUR_ZEPHYR_WEST_WORKSPACE
+west build zephyr-iolm/samples/demo -b YOUR_BOARD
+west flash
+```
+
+Where:
+
+- YOUR_ZEPHYR_WEST_WORKSPACE: Is the installation of your Zephyr SDK (i.e. `west init ..`). 
+  Note: This has only been tested with Zephyr revision v3.6.99 commit `34c84eccec0508b16f5001b20fa369f387d856df`
+- `YOUR_BOARD`: `esp32`, `nrf52833dk_nrf52833`
+
+## Expected Output
+
+```
+*** Booting Zephyr OS build ***
+[00:00:00.252,868] <inf> iol_master: IOLM Demo
+[00:00:00.252,868] <inf> iol_master: Total port cfg 2
+[00:00:00.252,929] <inf> iol_master: thread created iolink_handler_thread, prio 4
+[00:00:00.252,960] <inf> iol_master: Thread entry iolink_handler_thread
+[00:00:00.252,990] <inf> iol_master: os_event_create addr 2000a550
+[00:00:00.255,493] <inf> iol_master: Thread entry iolink_m_thread
+[00:00:00.255,584] <inf> iol_master: thread created iolink_m_thread, prio 3
+[00:00:00.255,737] <inf> iol_master: os_event_create addr 2000cd40
+[00:00:00.255,859] <inf> iol_master: Thread entry iolport1
+[00:00:00.255,920] <inf> iol_master: thread created iolport1, prio 2
+[00:00:00.255,981] <inf> iol_master: os_event_create addr 2000ced0
+[00:00:00.257,843] <inf> iol_master: os_event_create addr 2000cf68
+[00:00:00.257,965] <inf> iol_master: Thread entry iolport2
+[00:00:00.258,026] <inf> iol_master: thread created iolport2, prio 2
+[00:00:00.258,056] <inf> iol_master: os_event_create addr 2000d0f8
+[00:00:00.259,765] <inf> iol_master: iolink_handler started
+[00:00:00.386,138] <inf> iol_master: handle_smi_portevent (1): type = 0, event_code = 0xFF26, count = 0
+[00:00:00.386,169] <inf> iol_master: Port status changed
+[00:00:00.386,505] <inf> iol_master: iolink_start_port: Port 0: iolink device 0x0002b1 for VID 0x0136
+[00:00:00.386,535] <inf> iol_master: iolink_start_port: Port 0: Start done!
+[00:00:00.950,927] <inf> iol_master: handle_smi_portevent (2): type = 0, event_code = 0xFF26, count = 0
+[00:00:00.950,927] <inf> iol_master: Port status changed
+[00:00:00.951,263] <inf> iol_master: iolink_start_port: Port 1: iolink device 0x000243 for VID 0x0136
+[00:00:00.951,293] <inf> iol_master: iolink_start_port: Port 1: Start done!
+[00:00:01.006,591] <inf> iol_master: Port [2] PDIN Cnf 0b61
+[00:00:01.017,425] <inf> iol_master: Port [1] PDIN Cnf 00aa
+```

samples/demo/boards/esp32_devkitc_wrover_procpu.overlay

@@ -0,0 +1,16 @@
+&uart0 {
+	current-speed = <460800>;
+};
+
+&spi2 {
+	status = "okay";
+	cs-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
+    max:maxim14819@0 {
+		spi-max-frequency = <8000000>;
+		status = "okay";
+		irq-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
+        compatible = "iolm,maxim14819";
+        reg = <0x00>;
+		chip-address = <0x00>;
+    };
+};

samples/demo/boards/nrf52833dk_nrf52833.overlay

@@ -0,0 +1,39 @@
+&uart0 {
+	current-speed = <460800>;
+};
+
+&pinctrl {
+
+	spi1_default: spi1_default {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 0, 31)>,
+				<NRF_PSEL(SPIM_MOSI, 0, 30)>,
+				<NRF_PSEL(SPIM_MISO, 0,29)>;
+		};
+	};
+
+	spi1_sleep: spi1_sleep {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 0, 31)>,
+				<NRF_PSEL(SPIM_MOSI, 0, 30)>,
+				<NRF_PSEL(SPIM_MISO, 0, 29)>;
+			low-power-enable;
+		};
+	};
+};
+
+//#include <iolm/maxim14819.h>
+
+&spi1 {
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+    max:maxim14819@0 {
+		spi-max-frequency = <10000000>;
+		status = "okay";
+		irq-gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
+        compatible = "iolm,maxim14819";
+        reg = <0x00>;
+		chip-address = <0x00>;
+    };
+};

samples/demo/prj.conf

@@ -0,0 +1,13 @@
+# Copyright (c) 2024 Victor Chavez
+# SPDX-License-Identifier: GPL-3.0-or-later
+
+CONFIG_THREAD_NAME=y
+CONFIG_LOG=y
+CONFIG_IOLINK_LOG_LEVEL_DBG=y
+CONFIG_ASSERT=y
+CONFIG_MINIMAL_LIBC=y
+#CONFIG_LOG_BUFFER_SIZE=16384
+CONFIG_IOLINK=y
+CONFIG_IOLINK_MAIN_STACK_SIZE=1024
+CONFIG_IOLINK_DL_STACK_SIZE=1024
+CONFIG_IOLINK_NUM_PORTS=2