move simultaneous setup hold attr to open_chip script only if ran_wri…

…te_design. Previously this was done before final DB was written, causing hierarchical flow to fail

hammer/par/innovus/__init__.py

@@ -928,10 +928,6 @@ def write_regs(self) -> bool:
         return True
 
     def write_design(self) -> bool:
-        # Because implementation is done, enable report_timing -early/late and SDF writing
-        # without recalculating timing graph for each analysis view
-        self.append("set_db timing_enable_simultaneous_setup_hold_mode true")
-
         # Save the Innovus design.
         self.verbose_append("write_db {lib_name} -def -verilog".format(
             lib_name=self.output_innovus_lib_name
@@ -1026,6 +1022,11 @@ def run_innovus(self) -> bool:
         self.output.clear()
         assert super().do_pre_steps(self.first_step)
         self.append("read_db latest")
+        if self.ran_write_design:
+            # Because implementation is done, enable report_timing -early/late and SDF writing
+            # without recalculating timing graph for each analysis view
+            self.append("set_db timing_enable_simultaneous_setup_hold_mode true")
+
         self.write_contents_to_path("\n".join(self.output), self.open_chip_tcl)
 
         with open(self.open_chip_script, "w") as f: