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Merge branch 'master' into flowgraph
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bdngo committed Jan 4, 2024
2 parents bbb047f + 7aad633 commit b75b62a
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Showing 3 changed files with 20 additions and 7 deletions.
14 changes: 8 additions & 6 deletions hammer/par/innovus/__init__.py
Original file line number Diff line number Diff line change
Expand Up @@ -383,7 +383,9 @@ def place_bumps(self) -> bool:
self.append("deselect_bumps")
else:
self.append("assign_signal_to_bump -bumps \"Bump_{x}.{y}\" -net {n}".format(x=bump.x, y=bump.y, n=bump.name))
self.append("create_route_blockage {layer_options} \"{llx} {lly} {urx} {ury}\"".format(
self.append("create_route_blockage -name Bump_{x}_{y}_blockage {layer_options} \"{llx} {lly} {urx} {ury}\"".format(
x = bump.x,
y = bump.y,
layer_options="-layers {{{l}}} -rects".format(l=block_layer) if(self.version() >= self.version_number("181")) else "-cut_layers {{{l}}} -area".format(l=block_layer),
llx = "[get_db bump:Bump_{x}.{y} .bbox.ll.x]".format(x=bump.x, y=bump.y),
lly = "[get_db bump:Bump_{x}.{y} .bbox.ll.y]".format(x=bump.x, y=bump.y),
Expand Down Expand Up @@ -519,16 +521,16 @@ def power_straps(self) -> bool:

def place_opt_design(self) -> bool:
"""Place the design and do pre-routing optimization."""
self.verbose_append("place_opt_design")
return True

def clock_tree(self) -> bool:
"""Setup and route a clock tree for clock nets."""
if self.hierarchical_mode.is_nonleaf_hierarchical():
self.verbose_append('''
flatten_ilm
update_constraint_mode -name my_constraint_mode -ilm_sdc_files {sdc}
'''.format(sdc=self.post_synth_sdc), clean=True)
self.verbose_append("place_opt_design")
return True

def clock_tree(self) -> bool:
"""Setup and route a clock tree for clock nets."""
if len(self.get_clock_ports()) > 0:
# Ignore clock tree when there are no clocks
# If special cells are specified, explicitly set them instead of letting tool infer from libs
Expand Down
9 changes: 8 additions & 1 deletion hammer/vlsi/hammer_build_systems.py
Original file line number Diff line number Diff line change
Expand Up @@ -484,10 +484,17 @@ def build_makefile(driver: HammerDriver, append_error_func: Callable[[str], None
prereqs = " ".join(out_confs)
pstring = " ".join(["-p " + x for x in out_confs])
par_to_syn = textwrap.dedent("""
.PHONY: hier-par-to-syn-{node} redo-hier-par-to-syn-{node}
{syn_deps}: {prereqs}
\t$(HAMMER_EXEC) {env_confs} {pstring} -o {syn_deps} --obj_dir {obj_dir} hier-par-to-syn
hier-par-to-syn-{node}: {syn_deps}
redo-hier-par-to-syn-{node}:
\t$(HAMMER_EXEC) {env_confs} {pstring} -o {syn_deps} --obj_dir {obj_dir} hier-par-to-syn
""".format(syn_deps=syn_deps, prereqs=prereqs, env_confs=env_confs, pstring=pstring,
obj_dir=obj_dir))
obj_dir=obj_dir, node=node))

output += make_text.format(suffix="-"+node, mod=node, env_confs=env_confs, obj_dir=obj_dir, syn_deps=syn_deps,
par_to_syn=par_to_syn,
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4 changes: 4 additions & 0 deletions tests/test_build_systems.py
Original file line number Diff line number Diff line change
Expand Up @@ -135,6 +135,10 @@ def test_hier_makefile(self, tmpdir) -> None:
expected_targets.update({task + "-" + x for x in mods})
expected_targets.update({"redo-" + task + "-" + x for x in mods})

# Only non-leafs get a hier-par-to-syn target
expected_targets.update({"hier-par-to-syn-" + x for x in mods if x in {"TopMod"}})
expected_targets.update({"redo-hier-par-to-syn-" + x for x in mods if x in {"TopMod"}})

# Only non-leafs get a syn-*-input.json target
expected_targets.update({os.path.join(tmpdir, "syn-" + x + "-input.json") for x in mods if x in {"TopMod"}})
expected_targets.update({os.path.join(tmpdir, "sim-syn-" + x + "-input.json") for x in mods})
Expand Down

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