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fix(core): fix handover to bootloader #4221

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merged 1 commit into from
Sep 26, 2024
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@cepetr cepetr commented Sep 25, 2024

This PR fixes the firmware deadlock issue that occurred after the interaction-less update. Th bug was introduced in PR #4188, and only affects T and TS3 models.

The fix adds a transition from handler mode to thread mode before jumping to the bootloader.

@cepetr cepetr added core Trezor Core firmware. Runs on Trezor Model T and T2B1. T2B1 Trezor Safe 3 T2T1 Trezor Model T labels Sep 25, 2024
@cepetr cepetr self-assigned this Sep 25, 2024

"LDR R1, = 0xE000EF34 \n" // FPU->FPCCR
"LDR R0, [R1] \n"
"BIC R0, R0, #1 \n" // Clear LSPACT to suppress lazy
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from the description of LSPACT bit in programming manual:
Lazy state preservation active. Indicates whether lazy preservation of the floating-point state is active.
i would be expecting that this bit is managed by hardware and should be used by software as read only. Are you sure about this? For disabling of lazy stacking, i would expect LSPEN bit to be used, or by suppression do you mean that this should be only one time suppressed and this actually achieves it?

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Yes, it's kind of a one-time suppression.

If we hadn't done it here, the first FPU instruction used in the bootloader might cause lazy stacking and an unexpected overwrite of a portion of SRAM. There are some possible alternatives: 1) use any FPU instruction here instead of writing to FPU->FPPCR, which causes immediate stacking of FPU registers and clears the LSPACT bit, 2) possibly returning from handler mode with a different EXC_RETURN code...

I don't like it much either and I understand it looks a bit hacky.

@cepetr cepetr merged commit a5ddd13 into main Sep 26, 2024
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@cepetr cepetr deleted the cepetr/fix-handover-to-bl branch September 26, 2024 07:55
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core Trezor Core firmware. Runs on Trezor Model T and T2B1. T2B1 Trezor Safe 3 T2T1 Trezor Model T
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