jtag: shiftDR: (fix daisy chain) when more than one FPGA, a sequence …

…of '0' before and/or after must be sent instead of '1' (fix #189 and #133
trabucayre · Sep 17, 2023 · 94b6246 · 94b6246
1 parent 9810735
commit 94b6246
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/jtag.cpp b/src/jtag.cpp
@@ -345,7 +345,7 @@ int Jtag::shiftDR(const uint8_t *tdi, unsigned char *tdo, int drlen, tapState_t
 		if (bits_before > 0) {
 			int n = (bits_before + 7) / 8;
 			uint8_t tx[n];
-			memset(tx, 0xff, n);
+			memset(tx, 0x00, n);
 			read_write(tx, NULL, bits_before, 0);
 		}
 	}
@@ -363,7 +363,7 @@ int Jtag::shiftDR(const uint8_t *tdi, unsigned char *tdo, int drlen, tapState_t
 		if (bits_after > 0) {
 			int n = (bits_after + 7) / 8;
 			uint8_t tx[n];
-			memset(tx, 0xff, n);
+			memset(tx, 0x00, n);
 			read_write(tx, NULL, bits_after, 1);  // its the last force
 												  // tms high with last bit
 		}