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adder

Here are 125 public repositories matching this topic...

Telegram-Members-Adder

saifalisew1508 / Telegram-Members-Adder

Telegram Members Adding Software/Script Using Termux.

Updated Sep 24, 2024
Python

AbirHasan2005 / TelegramScraper

Using this tool you can easily add so many members from any group to your group. Less than 2 minutes. Super easy. Time saver. But this tool is only for educational purpose. You could be banned from Telegram. So be careful. Recommanded to use this tool only on Termux.

scraper termux telegram-group telegram-bots adder saver smsbot telegram-scraper-bot telegram-scraper

Updated Jul 30, 2023
Python

DenizShabani / telegramscraper

Scraper and adder for Telegram supporting multiple accounts at the same time. Adds via Telegram API and only by username. For adding via ID and not needing Telgram API contact me.

python scraper osint programming telegram script adder

Updated Mar 8, 2023
Python

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…

cpu processor simd verilog alu adder instruction-set-architecture cadence-virtuoso multiplier verilog-project processor-design

Updated Jul 17, 2022
Verilog

antonblanchard / vlsiffra

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

verilog booth vlsi adder multiplier physical-design dadda amaranth-hdl

Updated Sep 20, 2023
Python

nxbyte / Verilog-Projects

This repository contains source code for past labs and projects involving FPGA and Verilog based designs

simulator encoder decoder priority verilog xilinx testbenches multiplexer comparator adder system-verilog xilinx-vivado half-adder traffic-light-controller full-adder ripple-adder look-ahead-adder

Updated Oct 2, 2019
Verilog

Psingh12354 / HackerRank-Certification

HackerRank Certification Question

Updated Sep 6, 2023
Python

suoglu / Fixed-Floating-Point-Adder-Multiplier

16-bit Adder Multiplier hardware on Digilent Basys 3

fpga hardware verilog vivado fixed-point floating-point adder multiplier binary16

Updated Aug 3, 2023
Verilog

mongrelgem / Verilog-Adders

Implementing Different Adder Structures in Verilog

verilog hardware-designs adder verilog-hdl verilog-project

Updated Sep 3, 2019
Verilog

evilbream / TG_adder_with_proxy

Telegram Group Parser/Scraper and user Adder via id or username with proxy support

scraper proxy session adder telegram-scraper telegram-adder telegram-adding-tool

Updated Sep 16, 2024
Python

IamFlea / AdderCircuitGenerator

This script generates and analyzes prefix tree adders.

Updated Apr 9, 2021
Python

sumukhathrey / Verilog_ASIC_Design

Verilog for ASIC Design

counter hardware rtl verilog adder testbench gates sequence-detector hardware-modelling

Updated Sep 13, 2021
Verilog

RaulMurillo / Flo-Posit

Posit Arithmetic Cores generated with FloPoCo

vhdl adder posit unum multiplier posit-arithmetic flopoco

Updated Jun 25, 2024
VHDL

Damantha126 / TelegramScraper

Using this tool you can easily add so many members from any group to your group. Less than 2 minutes. Super easy. Time saver. But this tool is only for educational purpose. You could be banned from Telegram. So be careful. Recommanded to use this tool only on Termux.

scraper telegram and adder

Updated Jul 11, 2021
Python

mattvenn / instrumented_adder

Instrumenting adders to measure speed

asic hardware simulation adder ngspice sky130

Updated Jun 8, 2022
Verilog

KiranThomasCherian / VLSI-and-Computer-Architecture

Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim

pipeline verilog xilinx floating-point computer-architecture vlsi hardware-modules adder wallace-tree-multiplier iverilog floating-point-arithmetic pipelined carry-propogate-adders kogge-stone-adder sklansky-adder magic-tool gate-layout cmos-path-enumerator

Updated May 8, 2021
Verilog

BlackFoxTM / Tadder

Adds members of another group to another group

python telegram telegram-group adder

Updated Sep 9, 2022
Python

Performance-Analysis-of-Parallel-Prefix-Adders-Using-Zynq-7000-APSoC

neeraj1397 / Performance-Analysis-of-Parallel-Prefix-Adders-Using-Zynq-7000-APSoC

Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.

fpga verilog vivado prefix-tree adder xilinx-fpga xilinx-vivado zynq-7000 han-carlson brent-kung kogge-stone-adder ladner-fischer carry-look-ahead-adder ripple-carry-adder carry-save-adder prefix-adder

Updated Apr 13, 2021
Verilog

svelte-compose / svelte-compose

⚠️ MOVED: https://github.com/svelte-add/svelte-add/ ⚠️ Add different tools to your new or existing svelte / svelte-kit project

bootstrap composer kit svelte bulma adder tailwindcss mdsvex svelte-kit svelte-add svelte-compose

Updated May 5, 2024
TypeScript

seahore / turing-machine-emulator

一个命令行的图灵机演示模拟器

cpp11 turing-machine adder turing-machine-simulator introduction-to-computer-science educational-project whu

Updated Sep 26, 2020
C++

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