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@tomcl tomcl released this 20 Sep 20:41
· 663 commits to master since this release
v3.0.11
0af93e8

This is the production release for DECA 2022/23. There have been a lot of UI changes and additions since last year. So even though it is not tagged beta we expect a few issues, but hope for nothing major.

Please post issues if you discover any problems, or things you wish were better!

Current: v3.0.11 - see below for changes

Version Change Notes

v3.0.11

  • Bug Fix - simulation not advanced exception in waveform simulator when viewing ram
  • Bug Fix - < 32 bit counter component in some circumstances creates a simulation exception
  • Bug Fix - incorrect step simulator results for > 1000 steps

v3.0.10

  • Bug Fix #268 - changing the name of wire labels now correctly changes circuit error status
  • Feature. Radix selector is now displayed in step simulation with multi-bit viewers. (This was not true if there were no other multi-bit displays)
  • Improve split/merge component descriptions so they highlight vertical flipping to put MSB at top.

v3.0.9

  • Feature: allow _ in component and sheet names

v3.0.8

  • Fix bug which crashes waveform viewer in some cases

v3.0.7

  • Fix transient bug which causes waveforms to be blank
  • Improve waveform viewer help text

v3.0.6

  • Fix negative numbers display in sDec radix inside wave simulator
  • Make value column width adjustable in wave simulator

v3.0.5

  • Fix > 32 bit busses
  • Improve waveform simulation display

v3.0.4

Features:

  • Selected Truth tables can now be selected from selected components without also needing all internal connections
  • Truth-table columns can be moved left or right (See #254)

v3.0.3

Bug fixes:

v3.0.2

Minor changes:

  • Improve custom component auto-sizing based on ports positions and names
  • Improve theme colors (small changes)
  • Improve properties dialog focus

v3.0.2.beta1

  • fix #249 (still published as v3.0.1)

v3.0.1

  • Pull together all of the Summer work
  • Final changes from v3.0.0
    • Make bus compare constant definitions multi-radix consistent with constant definitions
    • Add shifts by numbers on busses to Verilog language accepted for Verilog components
    • Close some minor bugs from issues

Major changes from 2021/2022 - initial release notes

The code is now 36K lines (from 20K last year).

  • Better Schematic Editor - components can be rotated/flipped. Auto-routing works better and from any edge of a component. Manual routing combines with auto-routing smoothly. Smart snapping makes it easier to position components
  • Better Custom Components. The symbols instantiating subsheets can now have ports moved to any side of component with drag-and-drop UI. Components can have size scaled.
  • Sheets descriptions can now be added, This appears in Sheet properties window and info boxes on sheet menu for rapid exploration of designs
  • New components and additional properties on old components, fill in gaps.
    • Counter (optional enable, load).
    • N bit Adder (optional Cin, Cout)
    • N bit Not gate, AND, OR.
    • 2, 4, 8 input MUX and 2,4,8 output DEMUX to match. 2-input MUX has inputs switchable in position relative to select.
    • Bus spreader (1 bit -> N bits)
  • Verilog design entry. New editor window with great error messages allows combinational logic to be implemented as Verilog equations
  • New Waveform Viewer
    • One thing contentious - no scroll bar!
    • Can select any waveform on any sheet while simulating
    • Designs can be edited (any sheet) while running simulation, and simulation refreshed with a single click to see changes
    • UI is now consistent with Step simulator
    • Non-zero values on inputs allowed: default values are used and these can be set from Input properties or from step simulator
    • Components and connections highlight hovering over wave names (if the sheet the wave is on is selected
    • New hierarchical waveform selector (we think it is better, an it scales to very large designs)
    • Progressive simulation means simulation time is less noticeable
    • Progress bars for long waits in simulation or waveform generation (if 100s of waveforms are selected slowing this down) make a better UI
  • Update memory linking to files. Memories now have a decent UI for linking initial contents to files. File change auto-updates a design - and then single click in waveform simulator will show results of simulating with new data. Should help work in Spring
  • Truth table generator
    • Can show whole sheet or any selected part
    • Provides binary truth tables, with don't cares to simplify
    • Provides algebraic truth tables with good simplification of algebraic expressions
  • Minor negative - as result of algebraic evaluation the simulator is now about 30% slower than last year. A simulation overhaul with a much faster reimplementation is scheduled for 2023
  • Issie Stick supported. A one-click UI interfaces to external open source synthesis software to put designs onto a purpose-built EEE FPGA board so they drive real hardware. This is still experimental but the basic functionality now works.

Pretty well all the feature requests from last year have been implemented as well as a lot of things that make the UI more consistent and ergonomic.

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