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@JEMerrick JEMerrick released this 12 May 09:03
· 1662 commits to master since this release
v2.0.24
a1a5b1d

Beta Release

This release is the official beta release, after fixing the various bug reports and improving the features from the alpha release.

We will continue to fix bugs if any are reported and post new versions here if that happens.

Current version: 2.0.24

Changes in v2.0.24

  • New Features
    • Better manual routing: part manually routed wired remember their manual routing while still auto-routing endpoints and resetting to auto when topology changes.
    • Spinners improved on most long delays
    • Group move delay improved

Changes in 2.0.23

  • BugFixes
    • try again to fix simulation UI.

Changes in 2.0.22

  • BugFixes
    • Remove pesky q=0 assignments in synch RAM & ROM Verilog that crash some synthesis tools (but make Verilog simulation behave better
    • NB this fix will mean that synch RAM and ROM outputs are X during 1st cycle of a Verilog simulation. They are probably still guaranteed to be 0 in the synthesised logic (though this is not entirely clear). Normally your code would not use these 1st cycle outputs, so it does not matter.

Changes in v2.0.21

  • BugFixes
    • Fixed Verilog name generation for Issie names with strange characters
    • Fixed Verilog ROM generation (was causing syntax error)
    • Fixed Verilog multiple RAM or ROM modules

Changes in 2.0.19

  • BugFixes
    • Fixed a bug where for some values of number of steps the 'run simulation multiple steps' progress bar logic would crash the app.

Changes in v2.0.18

  • BugFixes
    • Fix case where a RAM created from a ram data file has data file changed externally. This now updates the RAM initialisation.

Changes in v2.0.17

  • BugFixes
    • Fix Verilog output from constants defined with negative numbers

Changes in v2.0.16

  • BugFixes
    • Make error highlighting work from step simulation, as should be. (Sorry this was not fixed earlier).

Changes in v2.0.15

  • BugFixes
    • Verilog output: XNOR crash mended.
    • Verilog output: Syntax for RAMs in synthesis.
    • Verilog output: invalid verilog names fixed

Changes in v2.0.14

  • Cosmetic changes only
  • No bug fixes
  • Features
    • Progress bar for long simulations
    • Simulation error messages made slightly more relevant.

Changes in v2.0.13

  • BugFixes
    • Fix syntax regression in Verilog output introduced in v2.0.12
    • Fix properties description of RAM function

Changes in v2.0.12

  • BugFixes
    • Verilog synthesis output is now correct (we think). Link to synthesis work-flow instructions posted. The (new) Verilog output functionality is now complete.
  • Features
    • Custom component ports are now ordered on creating a new instance
      • Existing instances stay as is
      • New instances have ports ordered by the last saved vertical position of the relevant port Input or Output component
      • Allows user ordering of ports on custom component symbols

Changes in v2.0.11

  • BugFixes
    • Verilog simulation output is now identical to issie output over all current tests
  • Features
    • Verilog output can be generated in either simulation or "ready to synthesise" form
    • Breaking Change. Synchronous RAMs during write cycle now put the previous cycle's read data (memOld[addrOld]) on dout. previous Issie simulation had put dout = din in a write cycle so that the read set up in the previous cycle was lost. The new spec is consistent with the RAMs synthesised, and more useful for pipelined designs, but the change in spec may alter correctness of designs if you rely on dout = din when synchronous RAM WEN=1. It is quite easy to create the old RAM spec from a new RAM and a MUX, so those affected could do that.

Changes in v2.0.10

  • BugFixes
    • Fix a bug where wire labels can sometimes cause waveform simulation (but not step simulation) to crash.

Changes in v2.0.9

  • Features
    • Very large simulation speed-up

Changes in v2.0.8

  • Features
    • Copy/Paste leaves Wire Labels without changing them. This will be wanted when the Label's driver is not pasted with the label, and not wanted in some other cases so it is not clear whether this is the best solution. But it is only a tiny code change so worth making given user feedback. Probably the final solution should be an algorithm that analyses the circuit being pasted and adapts to this. Feedback welcome.

Changes in v2.0.7

  • Features

    • Speed up very long/large simulations (taking more than 20s) by remembering only last 600 steps

  • BugFixes

    • Complete legacy simulation removal (not correctly done in 2.0.6)

Changes in v2.0.6

  • BugFixes
    • Fixes a problem where some large circuits caused legacy simulation to crash - by disabling all elements of legacy simulation.

Changes in v2.0.5

  • BugFixes
    • Fixed a bug where Wave Simulator wire selection would persist upon starting a Step Simulation

Changes in v2.0.4

  • BugFixes
    • Fixed errors in ROM and Asynchronous ROM components

Changes in 2.0.3

  • BugFixes
    • Fixed a bug where long simulations did not deliver correct results

Changes in 2.0.2

  • Features
    • "Goto" step in step simulation
  • Bugfixes
    • Fixed a bug where step simulation would be incorrect due to remembered previous simulation

Changes in 2.0.1

  • Features
    • Changed Ctrl+W from fit canvas to screen to fit circuit to screen
  • Bugfixes
    • Fixed a bug that caused the scroll position to be incorrect when changing sheets, causing the mouse to be offset
    • Fixed a bug that caused RAM viewer in wave simulator to be incorrect

Changes in v2.0.0 (from v1.9.0)

  • Features

    • Added automatic rescaling of custom components to fit port/label names
    • Added a popup to allow the user to automatically update custom components upon saving a sheet. Ports can be renamed without reconnection
    • Improved data entry and display for constants
    • Added better error reporting if opening a project on disk with wrong access permissions

  • Bugfixes

    • Fixed a bug that caused components with attributes such as width to not increment the automatic renaming properly
    • Fixed a bug that caused the mouse coordinates to be slightly north west making it difficult to click on wires / ports properly
    • Fixed a bug that caused the WaveSim error sidebar to automatically disappear
    • Fixed a bug that prevented error highlighting in the simulate tab
    • Fixed a bug that caused the components to not be movable after the circuit had a WaveSim error
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