Add missing Verilog statement termination

tomcl · Feb 19, 2024 · f1b7711 · f1b7711
1 parent 67f970a
commit f1b7711
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/Renderer/Simulator/Verilog.fs b/src/Renderer/Simulator/Verilog.fs
@@ -418,7 +418,7 @@ let getVerilogComponent (fs: FastSimulation) (fc: FastComponent) =
     | NotConnected -> ""
 
     | Not -> sprintf "assign %s = ! %s;\n" (outs 0) (ins 0)
-    | GateN (gateType, n) -> sprintf "assign %s = %s" (outs 0) (getVerilogNInputBinaryOp fc.FType ins)
+    | GateN (gateType, n) -> sprintf "assign %s = %s;\n" (outs 0) (getVerilogNInputBinaryOp fc.FType ins)
     | DFFE
     | RegisterE _ -> $"always @(posedge clk) %s{outs 0} <= %s{ins 1} ? %s{ins 0} : %s{outs 0};\n"
     | Counter _ -> $"always @(posedge clk) %s{outs 0} <= %s{ins 2} ? (%s{ins 1} ? %s{ins 0} : (%s{outs 0}+1'b1)) : %s{outs 0};\n"