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soc: xtensa: intel_adsp: Refine magic key initialization for ACE 1.5 #76

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soc: xtensa: intel_adsp: Refine magic key initialization for ACE 1.5 #76

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6 changes: 4 additions & 2 deletions soc/xtensa/intel_adsp/ace/multiprocessing.c
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Original file line number Diff line number Diff line change
Expand Up @@ -92,8 +92,10 @@ void soc_mp_init(void)
/* Set the core 0 active */
soc_cpus_active[0] = true;
#if CONFIG_ACE_VERSION_1_5
g_key_read_holder = INTEL_ADSP_ACE15_MAGIC_KEY;
sys_cache_data_flush_range(&g_key_read_holder, sizeof(g_key_read_holder));
volatile uint32_t *key_write_ptr = z_soc_cached_ptr(&g_key_read_holder);

*key_write_ptr = INTEL_ADSP_ACE15_MAGIC_KEY;
sys_cache_data_flush_range(key_write_ptr, sizeof(g_key_read_holder));
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If you want to write through the cache, use z_soc_uncached_ptr(). No need to pollute a cache line.

Also the volatile here is needless. You can use volatile to control compiler[1] re-ordering or removal of a memory access you want to happen. But no compiler is allowed to skip it entirely, if you write to a global variable it will be written.

[1] But not hardware! A really common mistake is trying to use volatile where you need a memory barrier instead. Obviously this is xtensa here, which is an in-order CPU. But just in general you should be really wary of volatile; it's probably not making the promises you want.

#endif /* CONFIG_ACE_VERSION_1_5 */
}

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