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[MTL-007] fix for HST power domain #74

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merged 2 commits into from
Dec 14, 2023
Merged

[MTL-007] fix for HST power domain #74

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1c22432
intel_adsp: ace: power: prevent hst domain power gating
tmleman Dec 13, 2023
980f757
intel_adsp: mtl: extra step for hst domain
tmleman Dec 13, 2023
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14 changes: 14 additions & 0 deletions drivers/power_domain/power_domain_intel_adsp.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,10 @@
#include <zephyr/pm/device_runtime.h>
#include <adsp_shim.h>

#if CONFIG_ACE_VERSION_1_5
#include <adsp_power.h>
#endif /* CONFIG_ACE_VERSION_1_5 */

#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(power_domain_intel_adsp, LOG_LEVEL_INF);

Expand All @@ -31,6 +35,16 @@
return -1;
}
} else {
#if CONFIG_ACE_VERSION_1_5
extern uint32_t g_key_read_holder;

if (bits->SPA_bit == INTEL_ADSP_HST_DOMAIN_BIT) {
volatile uint32_t* key_read_ptr = SRAM_TO_SRAM_ALIAS(&g_key_read_holder);

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POINTER_LOCATION 

drivers/power_domain/power_domain_intel_adsp.c:42  "foo* bar" should be "foo *bar"
uint32_t key_value = *key_read_ptr;
if (key_value != INTEL_ADSP_ACE15_MAGIC_KEY)

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LINE_SPACING 

drivers/power_domain/power_domain_intel_adsp.c:44  Missing a blank line after declarations
return -1;
}
#endif
sys_write16(sys_read16((mem_addr_t)&ACE_DfPMCCU.dfpwrctl) & ~(SPA_bit_mask),
(mem_addr_t)&ACE_DfPMCCU.dfpwrctl);
}
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15 changes: 15 additions & 0 deletions soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h
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Expand Up @@ -88,5 +88,20 @@
return (ACE_PWRSTS->dsphpxpgs & BIT(cpu_num)) == BIT(cpu_num);
}

/**
* @brief Retrieve node identifier for Intel ADSP HOST power domain.
*/
#define INTEL_ADSP_HST_DOMAIN_DTNODE DT_NODELABEL(hst_domain)

/**
* @brief Intel ADSP HOST power domain pointer.
*/
#define INTEL_ADSP_HST_DOMAIN_DEV DEVICE_DT_GET(INTEL_ADSP_HST_DOMAIN_DTNODE)

#define INTEL_ADSP_HST_DOMAIN_BIT DT_PROP(INTEL_ADSP_HST_DOMAIN_DTNODE, bit_position)

#define INTEL_ADSP_ACE15_MAGIC_KEY 0xFFFACE15

#define SRAM_TO_SRAM_ALIAS(address) ((__typeof__(address))((((uint32_t)(address)) & 0x1FFFFFFF) | 0x40000000))

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LONG_LINE 

soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h:105  line length of 110 exceeds 100 columns

#endif /* ZEPHYR_SOC_INTEL_ADSP_POWER_H_ */
10 changes: 10 additions & 0 deletions soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_power.h
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Expand Up @@ -88,4 +88,14 @@ static ALWAYS_INLINE bool soc_cpu_is_powered(int cpu_num)
return (ACE_PWRSTS->dsphpxpgs & BIT(cpu_num)) == BIT(cpu_num);
}

/**
* @brief Retrieve node identifier for Intel ADSP HOST power domain.
*/
#define INTEL_ADSP_HST_DOMAIN_DTNODE DT_NODELABEL(hst_domain)

/**
* @brief Intel ADSP HOST power domain pointer.
*/
#define INTEL_ADSP_HST_DOMAIN_DEV DEVICE_DT_GET(INTEL_ADSP_HST_DOMAIN_DTNODE)

#endif /* ZEPHYR_SOC_INTEL_ADSP_POWER_H_ */
14 changes: 14 additions & 0 deletions soc/xtensa/intel_adsp/ace/multiprocessing.c
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Expand Up @@ -9,6 +9,7 @@
#include <zephyr/sys/check.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/pm/pm.h>
#include <zephyr/pm/device_runtime.h>

#include <soc.h>
#include <adsp_boot.h>
Expand All @@ -25,6 +26,11 @@

#define ACE_INTC_IRQ DT_IRQN(DT_NODELABEL(ace_intc))

#if CONFIG_ACE_VERSION_1_5
__attribute__((__aligned__(CONFIG_DCACHE_LINE_SIZE))) uint32_t g_key_read_holder;

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PREFER_ALIGNED 

soc/xtensa/intel_adsp/ace/multiprocessing.c:30  __aligned(size) is preferred over __attribute__((aligned(size)))
__attribute__((__aligned__(CONFIG_DCACHE_LINE_SIZE))) unsigned alignment_dummy[0];

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UNSPECIFIED_INT 

soc/xtensa/intel_adsp/ace/multiprocessing.c:31  Prefer 'unsigned int' to bare use of 'unsigned'

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PREFER_ALIGNED 

soc/xtensa/intel_adsp/ace/multiprocessing.c:31  __aligned(size) is preferred over __attribute__((aligned(size)))
#endif /* CONFIG_ACE_VERSION_1_5 */

static void ipc_isr(void *arg)
{
uint32_t cpu_id = arch_proc_id();
Expand Down Expand Up @@ -79,8 +85,16 @@
IDC[i].agents[0].ipc.ctl = BIT(0); /* IPCTBIE */
}

int ret = pm_device_runtime_get(INTEL_ADSP_HST_DOMAIN_DEV);
ARG_UNUSED(ret);

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LINE_SPACING 

soc/xtensa/intel_adsp/ace/multiprocessing.c:89  Missing a blank line after declarations
__ASSERT(ret == 0, "HST power domain resume operation failed.");

/* Set the core 0 active */
soc_cpus_active[0] = true;
#if CONFIG_ACE_VERSION_1_5
g_key_read_holder = INTEL_ADSP_ACE15_MAGIC_KEY;
sys_cache_data_flush_range(&g_key_read_holder, sizeof(g_key_read_holder));
#endif /* CONFIG_ACE_VERSION_1_5 */
}

#ifdef CONFIG_ADSP_IMR_CONTEXT_SAVE
Expand Down
14 changes: 14 additions & 0 deletions soc/xtensa/intel_adsp/ace/power.c
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Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@
*/
#include <zephyr/kernel.h>
#include <zephyr/pm/pm.h>
#include <zephyr/pm/device_runtime.h>
#include <zephyr/device.h>
#include <zephyr/debug/sparse.h>
#include <zephyr/cache.h>
Expand Down Expand Up @@ -235,6 +236,8 @@
{
ARG_UNUSED(substate_id);
uint32_t cpu = arch_proc_id();
int ret = 0;
ARG_UNUSED(ret);

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LINE_SPACING 

soc/xtensa/intel_adsp/ace/power.c:240  Missing a blank line after declarations

/* save interrupt state and turn off all interrupts */
core_desc[cpu].intenable = XTENSA_RSR("INTENABLE");
Expand Down Expand Up @@ -297,6 +300,8 @@
hpsram_mask = (1 << ebb_banks) - 1;
#endif /* CONFIG_ADSP_POWER_DOWN_HPSRAM */
/* do power down - this function won't return */
ret = pm_device_runtime_put(INTEL_ADSP_HST_DOMAIN_DEV);
__ASSERT(ret == 0, "HST power domain suspend operation failed.");
power_down(true, uncache_to_cache(&hpsram_mask),
true);
} else {
Expand All @@ -312,6 +317,9 @@
battr |= (DSPBR_BATTR_LPSCTL_RESTORE_BOOT & LPSCTL_BATTR_MASK);
DSPCS.bootctl[cpu].battr = battr;
}

ret = pm_device_runtime_put(INTEL_ADSP_HST_DOMAIN_DEV);
__ASSERT(ret == 0, "HST power domain suspend operation failed.");
power_gate_entry(cpu);
} else {
__ASSERT(false, "invalid argument - unsupported power state");
Expand All @@ -324,6 +332,12 @@
ARG_UNUSED(substate_id);
uint32_t cpu = arch_proc_id();

if (cpu == 0) {
int ret = pm_device_runtime_get(INTEL_ADSP_HST_DOMAIN_DEV);
ARG_UNUSED(ret);

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LINE_SPACING 

soc/xtensa/intel_adsp/ace/power.c:337  Missing a blank line after declarations
__ASSERT(ret == 0, "HST power domain resume operation failed.");
}

if (state == PM_STATE_SOFT_OFF) {
/* restore clock gating state */
DSPCS.bootctl[cpu].bctl |=
Expand Down
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