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all: sim | ||
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sim: main.o Core.o Memory.o PipelineRegister.o | ||
g++ main.o Core.o Memory.o PipelineRegister.o -o sim | ||
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main.o: main.cpp Core.h Memory.h Register.h PipelineRegister.h | ||
g++ -c main.cpp | ||
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Core.o: Core.cpp Core.h Memory.h Register.h PipelineRegister.h | ||
g++ -c Core.cpp | ||
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Memory.o: Memory.cpp Memory.h | ||
g++ -c Memory.cpp | ||
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PipelineRegister.o: PipelineRegister.cpp PipelineRegister.h Register.h | ||
g++ -c PipelineRegister.cpp | ||
sim: | ||
g++ -g -I include src/main.cpp src/Core.cpp src/Memory.cpp src/PipelineRegister.cpp -o ./bin/sim | ||
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clean: | ||
rm *.o sim | ||
rm -f bin/sim |
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======================================================== | ||
Functional & Pipeline Simulator for simpleRISC processor | ||
======================================================== | ||
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README | ||
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Table of contents | ||
1. Directory Structure | ||
2. How to build | ||
3. How to execute | ||
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Directory Structure: | ||
-------------------- | ||
CSL211-Project | ||
| | ||
|- bin | ||
| | ||
|- sim | ||
|- include | ||
| | ||
|- Core.h | ||
|- Memory.h | ||
|- PipelineRegister.h | ||
|- Register.h | ||
|- src | ||
|- main.cpp | ||
|- Core.cpp | ||
|- Memory.cpp | ||
|- PipelineRegister.cpp | ||
|- test | ||
|- simple_add.mem | ||
|- fib.mem | ||
|- array_add.mem | ||
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How to build | ||
------------ | ||
For building: | ||
$make | ||
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For cleaning the project: | ||
$make clean | ||
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How to execute | ||
-------------- | ||
To run the functional program | ||
./bin/sim test/<INPUT MEM FILE> | ||
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To run the pipeline program | ||
./bin/sim test/<INPUT MEM FILE> 1 | ||
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To export the result for a test file eg. array_sum.mem with pipeline | ||
./bin/sim test/array_sum.mem 1 > output | ||
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The code generates a DATA_OUT.mem i.e. the complete memory at the termination of program | ||
and a STATE_OUT.mem i.e. complete state of processor at the termination of program. | ||
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The output contains instruction by instruction work done in each cycle in all stages namely - | ||
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1. FETCH | ||
2. DEOCDE | ||
3. EXECUTE | ||
4. MEMORY ACCESS | ||
5. WRITEBACK | ||
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Developed by | ||
NAMAN GOYAL, 2015CSB1021 | ||
EESHAAN SHARMA, 2015CSB1011 | ||
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