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isasim: ALU long immediate
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schoeberl committed Sep 27, 2016
1 parent b59aebd commit 90cde7a
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Showing 3 changed files with 8 additions and 7 deletions.
2 changes: 1 addition & 1 deletion asm/ALUl.s
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
# long immediate instructions

.word 180;
addi r1 = r0, 255; # first instruction not executed 0
addi r1 = r0, 255;
addi r1 = r0, 2; # r1 = 2
add r1 = r1, 65536; # r1 = 65538
add r2 = r0, 65536; # r2 = 65536
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7 changes: 4 additions & 3 deletions isasim/src/main/scala/PatSim.scala
Original file line number Diff line number Diff line change
Expand Up @@ -139,6 +139,7 @@ class PatSim(instructions: Array[Int]) {
case AluReg => (alu(func, op1, op2), true, false, pcNext)
case _ => throw new Exception("OpcodeExt " + opc + " not (yet) implemented")
}
case AluLongImm => (alu(func, op1, longImm), true, false, pcNext+1)
case Branch => throw new Exception("Branch")
case BranchCf => (0, false, false, imm22)
// case Branch => (0, false, if (compare(funct3, rs1Val, rs2Val)) pc + imm else pcNext)
Expand All @@ -162,15 +163,15 @@ class PatSim(instructions: Array[Int]) {
reg(rd) = result._1
}

// increment program counter
pc = result._4

// Quick hack for the halt instruction
if (result._4 == 0) {
halt = true
}

log

// increment program counter
pc = result._4
}

def error(s: String) {
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6 changes: 3 additions & 3 deletions tools/java/src/util/CompareScala.java
Original file line number Diff line number Diff line change
Expand Up @@ -156,13 +156,13 @@ public static void main(String[] args) throws Exception {
if (hs.hasNext(passedExitPattern)) {
break;
}
// unsigned int output from Scala
pc = (int) hs.nextLong();
// signed int output from Scala
pc = (int) hs.nextInt();
hs.next(); // skip '-'
boolean change = false;
for (int i = 0; i < 32; ++i) {
// To skip register names and switch to hex see compare with pasim
hsReg[i] = (int) hs.nextLong();
hsReg[i] = (int) hs.nextInt();
if (hsReg[i] != hsRegOld[i]) {
change = true;
cntNoChange = 0;
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