This document captures the status of various cores and SoCs that endeavor to implement the RISC-V specification. Note that none of these cores/SoCs have passed the in-development RISC-V compliance suite.
Please add to the list and fix inaccuracies.
| Name | Supplier | Links | Priv. spec | User spec | Primary Language | License |
|---|---|---|---|---|---|---|
| RV32EC_P2 | IQonIC Works | Website | 1.11 | RV32E[M]C/RV32I[M]C | SystemVerilog | IQonIC Works Commercial License |
| RV32IC_P5 | IQonIC Works | Website | 1.11 | RV32I[M][N][A]C | SystemVerilog | IQonIC Works Commercial License |
| RV32EC_FMP5 | IQonIC Works | Website | Custom | RV32EC | SystemVerilog | IQonIC Works Commercial License |
| rocket | SiFive, UCB Bar | GitHub | 1.11-draft | 2.3-draft | Chisel | BSD |
| freedom | SiFive | GitHub | 1.11-draft | 2.3-draft | Chisel | BSD |
| Berkeley Out-of-Order Machine (BOOM) | Esperanto, UCB Bar | GitHub | 1.11-draft | 2.3-draft | Chisel | BSD |
| ORCA | VectorBlox | GitHub | RV32IM | VHDL | BSD | |
| RI5CY | ETH Zurich, Università di Bologna | GitHub | RV32IMC | SystemVerilog | Solderpad Hardware License v. 0.51 | |
| Ibex (formerly Zero-riscy) | lowRISC | GitHub | 1.11 | RV32I[M]C/RV32E[M]C | SystemVerilog | Apache 2.0 |
| Ariane | ETH Zurich, Università di Bologna | Website,GitHub | 1.11-draft | RV64GC | SystemVerilog | Solderpad Hardware License v. 0.51 |
| Riscy Processors | MIT CSAIL CSG | Website,GitHub | Bluespec | MIT | ||
| RiscyOO | MIT CSAIL CSG | GitHub | 1.10 | RV64IMAFD | Bluespec | MIT |
| Lizard | Cornell CSL BRG | GitHub | RV64IM | PyMTL | BSD | |
| Minerva | LambdaConcept | GitHub | 1.10 | RV32I | nMigen | BSD |
| OPenV/mriscv | OnChipUIS | GitHub | RV32I(?) | Verilog | MIT | |
| VexRiscv | SpinalHDL | GitHub | RV32I[M][C] | SpinalHDL | MIT | |
| Roa Logic RV12 | Roa Logic | GitHub | 1.9.1 | 2.1 | SystemVerilog | Non-Commercial License |
| SCR1 | Syntacore | GitHub | 1.10 | 2.2, RV32I/E[MC] | SystemVerilog | SHL v. 2.0 |
| SCR3 | Syntacore | Website | 1.10 | RV[32/64]IMC[A], 2.2, milticore | SystemVerilog | commercial |
| SCR4 | Syntacore | Website | 1.10 | RV[32/64]IMCF[DA], 2.2, milticore | SystemVerilog | commercial |
| SCR5 | Syntacore | Website | 1.10 | RV[32/64]IMC[FDA], 2.2, milticore | SystemVerilog | commercial |
| SCR7 | Syntacore | Website | 1.10 | RV64GC, 2.2, milticore | SystemVerilog | commercial |
| Hummingbird E200 | Bob Hu | GitHub | 1.10 | 2.2, RV32IMAC | Verilog | Apache 2.0 |
| Shakti | IIT Madras | Website,GitLab | 1.11 | 2.2, RV64IMAFDC | Bluespec | BSD |
| ReonV | Lucas Castro | GitHub | VHDL | GPL v3 | ||
| PicoRV32 | Clifford Wolf | GitHub | RV32I/E[MC] | Verilog | ISC | |
| MR1 | Tom Verbeure | GitHub | RV32I | SpinalHDL | Unlicense | |
| SERV | Olof Kindgren | GitHub | RV32I | Verilog | ISC | |
| SweRV EH1 | Western Digital Corporation | GitHub | RV32IMC | SystemVerilog | Apache 2.0 | |
| Reve-R | Gavin Stark | GitHub | 1.10 | RV32IMAC | CDL | Apache 2.0 |
| Bk3 | Codasip | Website | 1.10 | RV32EMC / RV32IM[F]C | Verilog | Codasip EULA |
| Bk5 | Codasip | Website | 1.10 | RV32IM[F]C / RV64IM[F]C | Verilog | Codasip EULA |
| Bk7 | Codasip | Website | 1.10 | RV64IMA[F][D][C] | Verilog | Codasip EULA |
| DarkRISCV | Darklife | GitHub | most of RV32I | Verilog | BSD | |
| RPU | Domipheus Labs | GitHub | RV32I | VHDL | Apache 2.0 | |
| RV01 | Stefano Tonello | OpenCores | 1.7 | 2.1, RV32IM | VHDL | LPGL |
| N22 | Andes | Website | 1.11 | RV32IMAC/EMAC + Andes V5/V5e ext. | Verilog | Andes FreeStart IPEA |
| N25F | Andes | Website | 1.11 | RV32GC + Andes V5 ext. | Verilog | Andes Commercial License |
| D25F | Andes | Website | 1.11 | RV32GCP + Andes V5 ext. | Verilog | Andes Commercial License |
| A25 | Andes | Website | 1.11 | RV32GCP + SV32 + Andes V5 ext. | Verilog | Andes Commercial License |
| A25MP | Andes | Website | 1.11 | RV32GCP + SV32 + Andes V5 ext. + Multi-core | Verilog | Andes Commercial License |
| NX25F | Andes | Website | 1.11 | RV64GC + Andes V5 ext. | Verilog | Andes Commercial License |
| AX25 | Andes | Website | 1.11 | RV64GCP + SV39/48 + Andes V5 ext. | Verilog | Andes Commercial License |
| AX25MP | Andes | Website | 1.11 | RV64GCP + SV39/48 + Andes V5 ext. + Multi-core | Verilog | Andes Commercial License |
| Instant SoC | FPGA Cores | Website | RV32IM | VHDL | Free Non Commercial |
| Name | Supplier | Links | Core | License |
|---|---|---|---|---|
| Rocket Chip | SiFive, UCB BAR | GitHub,Simulator | Rocket | BSD |
| LowRISC | lowRISC | GitHub | RV32IM | BSD |
| PULPino | ETH Zurich, Università di Bologna | Website,GitHub | RI5CY, Zero-riscy | Solderpad Hardware License v. 0.51 |
| PULPissimo | ETH Zurich, Università di Bologna | Website,GitHub | RI5CY, Zero-riscy | Solderpad Hardware License v. 0.51 |
| Ariane SoC | ETH Zurich, Università di Bologna | Website,GitHub | Ariane | Solderpad Hardware License v. 0.51 |
| OPENPULP | ETH Zurich, Università di Bologna | Website,GitHub | RI5CY, Zero-riscy | Solderpad Hardware License v. 0.51 |
| HERO | ETH Zurich, Università di Bologna | Website,GitHub | RI5CY, Zero-riscy | Solderpad Hardware License v. 0.51 |
| OpenPiton + Ariane | Princeton Parallel Group, ETH Zurich, Università di Bologna | Website,GitHub | Ariane | Solderpad Hardware License v. 0.51, BSD |
| Briey | SpinalHDL | GitHub | VexRiscv | MIT |
| Riscy | AleksandarKostovic | GitHub | RV64I | MIT |
| Raven | RTimothyEdwards, mkkassem (efabless.com) | GitHub | PicoRV32 | ISC |
| PicoSoC | Clifford Wolf | GitHub | PicoRV32 | ISC |
| Icicle | Graham Edgecombe | GitHub | RV32I | ISC |
| MIV RV32IMA L1 AHB | Microchip | Documentation, IDE, Development Environment | Rocket RV32IMA | Apache 2.0 |
| MIV RV32IMA L1 AXI | Microchip | Documentation, IDE, Development Environment | Rocket RV32IMA | Apache 2.0 |
| MIV RV32IMAF L1 AHB | Microchip | Documentation, IDE, Development Environment | Rocket RV32IMAF | Apache 2.0 |
| FreeStart AE250 | Andes | Website | N22 | Andes FreeStart: Free for Evaluation |
| Standard AE250 | Andes | Website, IDE | N22 | Andes Commerical License |
| AE350 | Andes | Website, IDE | N25F, D25F, A25, A25MP, NX25F, AX25, AX25MP | Andes Commerical License |
| SCR1 SDK | Syntacore | GitHub | SCR1, SCRx | SHL 2.0 |
Include a chip if it has been fabricated and is either available for sale, available for preorder, or running production workloads internally, and if it has at least one RISC-V hard core (no FPGAs, but non-"SoC" products with controller cores are allowed).
| Name | Supplier | Links | Core | ISA | OS | Devkit | Availability |
|---|---|---|---|---|---|---|---|
| FE310-G000 | SiFive | Datasheet | E31 | RV32IMAC | RTOS | HiFive1 | public since 2016Q4 |
| FE310-G002 | SiFive | Product page | E31 | RV32IMAC | RTOS | HiFive1 Rev B | announced 2019Q1, available for preorder |
| Freedom U540 | SiFive | Product page | U54 (4 cores), E51 (1 management core) | RV64GC (application cores), RV64IMAC (management core) | Linux | HiFive Unleashed development board | public since 2018Q1 |
| GAP8 | GreenWaves Technologies | Product page | PULP / 1 + 8 RI5CY | RV32IMC (+ Priviledged and custom ISA extensions) | RTOS | GAPuino development board | public since 2018Q1 |
| K210 | Kendryte | Product page, Datasheet, GitHub | K210 | RV64GC | RTOS | KD233 development board, Sipeed MAIX/M1 development boards | public since 2018Q4 |
| RV32M1 | NXP | Reference Manual and Datasheet | RI5CY + Zero RI5CY + Arm Cortex M4F + Arm Cortex M0+ | RV32IMC | RTOS | VEGAboard | available for preorder as of 2018Q4 |
| RavenRV32 | efabless | Datasheet, GitHub | PicoRV32 | RV32IMAC | RTOS | RavenRV32 DevKit | Limited Quantity |
| PolarFire SoC | Microchip | Product Page, IDE with Renode platform | U54 (4 cores), E51 (management core) | RV64GC(U54), RV64IMAC(E51) | Linux | HiFive Unleashed Expansion Board, PolarFire SoC | HiFive Unleased Expansion Board - Q2 2018, PolarFire Soc – announced December 2018 |