Chip to chip communication

Introduction

We have Parallella and Liquit Router board, so we need to communicate Zynq (on Parallella) and Artix (LR) chips through GPIO's in order to access EMMC cards( which are placed on LR and connected to Artix FPGA) from Parallella side.

Implementation

First step of implementation of SerDes is to design simple one. Where will be occupied existing 10 pins (5 LVDS) between the Parallella and Liquid Router. The simple SerDes will transfer the signals of 1 eMMC controller, where eMMC HC will be in SDR mode 4bit data bus. The Architecture of design like in picture below:

Multiplexing rate 4:1 wires without LVDS: 1 wire SD_CLOCK + 1 wire RESET 1 lvds pair for output data 1 lvds pair for input data 2 lvds pair for TX/RX clock

To improve this simple design we may consider ways below:

1- We may require more LVDS

2- We may reduce used pins number, by changing the techniques of transfer. We may remove reset pin, TX & RX clock and we may change the bitslip operations for synchronization.

3- We may use some compressing techniques or something like this, this require some research on it (this option not promising effective solution)

Phases of eMMC HC SerDes:

1. Test sending 1 eMMC HC's signals in SDR 4 bit mode (between parallella & LR)

• Test simple loopback single line with Parallella (AXI GPIO) and LR(connect input&output with wire)
• Test simple loopback single line with Parallella (OSERDES/ISERDES) and LR(connect input&output with wire)
• Test simple loopback LVDS line with Parallella (PLL_base/OSERDES/ISERDES/OBUFDS/IBUFDS) and LR(connect input&output with IBUFDS/OBUFDS)
• Test loopback on LVDS line with Parallella (PLL_base/OSERDES/ISERDES/OBUFDS/IBUFDS) and LR(IBUFDS/PLL_base/ISERDES/OSERDES/OBUFDS)
• Test loopback for maximum speed on LVDS line with Parallella (PLL_base/OSERDES/ISERDES/OBUFDS/IBUFDS) and LR(IBUFDS/PLL_base/ISERDES/OSERDES/OBUFDS) -> working on 200Mhz in DDR mode with 8:1 serialization
• Needed to send command line and sd_clock of eMMC
• Needed to send data line of eMMC
• Test and debug CMD line synchronization between the Parallella & LR's side of eMMC HC

• • SD clock and CMD line signals sync
• • ISERDES/OSERDES & CMD line output sync
• • eMMC connection pins signals test (Voltage, shortcut, etc)
• • eMMC in CMD layer implemented delay controller between the Output & Input

• Test and debug Data line synchronization between the Parallella & LR's side of eMMC HC

• • eMMC in Data layer implemented delay controller between the Output & Input, for token response

• Put some identification mode where Artix board is present or not

2. Know the limits of eMMC read/write performance, mining where we can minimize the eMMC HC signals

• Maximum high speed -> 320 MHz on DDR mode of ISERDES/OSERDES 8:1 serialization
• Needed to make some research how to synchronize the high speed with low speed (SerDes will work on high speed ~350Mhz and eMMC will work on 50Mhz), maybe using some FIFO's

3. Make better eMMC LVDS communication where will be decided gaining storage space or performance
4. In new design of LR increase the number of LVDS signals

• The number of LVDS pairs increased into 7 pairs, where it 's 14 single line