Advanced DMA

###Description Host Controller Standard Specification Version 2.00 defines the ADMA (Advanced DMA) transfer algorithm. The DMA algorithm defined in the SD Host Controller Standard Specification Version 1.00 is called SDMA (Single Operation DMA). SDMA had disadvantage that DMA Interrupt generated at every page boundary disturbs CPU to reprogram the new system address. This SDMA algorithm forms a performance bottleneck by interruption at every page boundary. ADMA adopts scatter gather DMA algorithm so that higher data transfer speed is available. The Host Driver can program a list of data transfers between system memory and SD card to the Descriptor Table before executing ADMA. It enables ADMA to operate without interrupting the Host Driver. Furthermore, ADMA can support not only 32-bit system memory addressing but also 64-bit system memory addressing. The 32-bit system memory addressing uses lower 32-bit field of 64-bit address registers. Support of SDMA and ADMA are optional for the Host Controller.
There are two types of ADMA; ADMA1 and ADMA2. ADMA1 can support data transfer of only 4KB aligned data in system memory. ADMA2 improves the restriction so that data of any location and any size can be transferred in system memory. The format of Descriptor Table is different between them. The Host Controller Specification Ver2.00 defines ADMA2 as standard ADMA and recommends supporting ADMA2 rather than ADMA1. DMA mode ADMA1 is not supported in Standard Host Controller versions 3.0 and latter. When the term "ADMA" is used, it means ADMA2.
###ADMA work principles Figure 3

Figure1 shows block diagram of ADMA2. The Descriptor Table is created in system memory by the Host Driver. 32-bit Address Descriptor Table is used for the system with 32-bit addressing. Each descriptor line (one executable unit) consists with address, length and attribute field. The attribute specifies operation of the descriptor line. ADMA2 includes SDMA, State Machine and Registers circuits. ADMA2 does not use 32-bit SDMA System Address Register (offset 0) but uses the 64-bit Advanced DMA System Address register (offset 058h) for descriptor pointer. Writing Command register triggers off ADMA2 transfer. ADMA2 fetches one descriptor line and execute it. This procedure is repeated until end of descriptor is found (End=1 in attribute).

Figure2 shows a typical ADMA2 descriptor program. The Host Driver describes the Descriptor Table with each slice is placed somewhere in contiguous system memory. The Host Driver describes the Descriptor Table with set of address, length and attributes. Each sliced data is transferred in turns as programmed in descriptor. ####Data Address and Data Length Requirements There are 3 requirements to program the descriptor:

• The minimum unit of address is 4 bytes.
• The maximum data length of each descriptor line is less than 64KB.
• Total Length = Length 1 + Length 2 + Length 3 + ... + Length n = multiple of Block Size.

If total length of a descriptor were not multiple of block size, ADMA2 transfer might not be terminated. In this case, the transfer should be aborted by data timeout.

Block Count register limits the maximum of 65535 blocks transfer. If ADMA2 operation is less than or equal 65535 blocks transfer, Block Count register can be used. In this case, total length of Descriptor Table shall be equivalent to multiply block size and block count. If ADMA2 operation is more than 65535 blocks transfer, Block Count Register shall be disabled by setting 0 to Block Count Enable in the Transfer Mode Register. In this case, length of data transfer is not designated by block count but Descriptor Table. Therefore, the timing of detecting the last block on SD bus may be different and it affects the control of Read Transfer Active, Write Transfer Active and DAT line Active in the Present State register. In case of read operation, several blocks may be read more than required. The Host Driver shall ignore out of range error if the read operation is for the last block of memory area.
Figure 3

Figure3 shows the definition of 32-bit Address Descriptor Table. One descriptor line consumes 64-bit (8-byte) memory space. Attribute is used to control descriptor. 3 action symbols are specified. "Nop" operation skips current descriptor line and fetches next one. "Tran" operation transfers data designated by address and length field. "Link" operation is used to connect separated two descriptors. The address field of link points to next Descriptor Table. The combination of Act2=0 and Act1=1 is reserved and defined the same operation as Nop. A future version of controller may use this field and redefine a new operation. 32-bit address is stored in the lower 32-bit of 64-bit address registers. Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0) for 32-bit address descriptor table. Table 1 shows the definition of length field in the Descriptor Table.

Length Field	Value of length
0000h	65536 Bytes
0001h	1 Byte
0002h	2 Bytes
......	......
FFFFh	65535 Bytes
Table 1: ADMA2 Length Field
###ADMA Implementation
ADMA is implemented as individual module. Figure4 shows state diagram of ADMA2. 4 states are defined; Fetch Descriptor state, Change Address state, Transfer Data state, and Stop ADMA state. Operation of each state is explained in Table2.

State Name	Operation
ST_FDS(Fetch Descriptor)	ADMA2 fetches a descriptor line and set parameters in internal registers. Next go to ST_CADR state.
ST_CADR(Change Address)	Link operation loads another Descriptor address to ADMA System Address register. In other operations, ADMA System Address register is incremented to point next descriptor line. If End=0, go to ST_TFR state. ADMA2 shall not be stopped at this state even if some errors occur.
ST_TFR(Transfer Data)	Data transfer of one descriptor line is executed between system memory and SD card. If data transfer continues (End=0) go to ST_FDS state. If data transfer completes, go to ST_STOP state.
ST_STOP(Stop DMA)	ADMA2 stays in this state in following cases: (1) After Power on reset or software reset. (2) All descriptor data transfers are completed. If a new ADMA2 operation is started by writing Command register, go to ST_FDS state.
Table 2: ADMA States

ADMA2 does not support suspend / resume function but stop and continue are available. When the Stop At Block Gap Request in the Block Gap Control register is set during the ADMA2 operation, the Block Gap Event Interrupt is generated when ADMA2 is stopped at block gap. The Host Controller shall stop ADMA2 read operation by using Read Wait or stopping SD Clock. While stopping ADMA2, any SD commands cannot be issued. (In case of Host Controller version 1.00, the Stop At Block Gap Request can be set only when the card supports the Read Wait).

Error occurrence during ADMA2 transfer may stop ADMA2 operation and generate an ADMA Error Interrupt. The ADMA Error State field in the ADMA Error Status register holds state of ADMA2 stopped. The host driver can identify the error descriptor location by the following method: If ADMA stopped at ST_FDS state, the ADMA System Address register points the error descriptor line. If ADMA stopped at ST_TFR or ST_STOP state, the ADMA System Address register points the next location of error descriptor line. By this reason, ADMA2 shall not stop at ST_CADR state.