A question on cycle counts of CFU unit

[mahdi259]

Sorry, I have two questions.
1- Does the 4 clock cycles that you mentioned for a fast multiplication in datasheet include fetch and write back stages?
2- Does CPU perform fetch and write back of CFU similar to multiplication (each in one clock cycle)?

[mahdi259]

Btw, I think that fast multiplier consumes 3 clock cycles and it may require 5 cycles including fetch and write back.

neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd

Lines 182 to 183 in e72c254

	mul.dsp_x <= signed((rs1_i(rs1_i'left) and ctrl.rs1_is_signed) & rs1_i);
	mul.dsp_y <= signed((rs2_i(rs2_i'left) and ctrl.rs2_is_signed) & rs2_i);

neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd

Line 185 in e72c254

mul.prod <= std_ulogic_vector(mul.dsp_z(63 downto 0));

neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd

Line 309 in e72c254

res_o <= mul.prod(31 downto 0);

[stnolting]

1- Does the 4 clock cycles that you mentioned for a fast multiplication in datasheet include fetch and write back stages?

Yes, it does. Here is a screenshot from simulating a multiplication instruction:

0x03558933 = mul x18, x11, x21

Execution takes 4 cycles (blue marker to yellow marker) requiring a single multi-cycle ALU stall cycle.

2- Does CPU perform fetch and write back of CFU similar to multiplication (each in one clock cycle)?

Short answer: yes.

Every instruction requires a fetch (or actually, a dispatch as the fetching is done independently of instruction execution). The write-back is "implicit" - there is no actual execution stage for this.

[mahdi259]

Exactly. Thanks a lot.
This one is combinational assignment.

neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd

Line 309 in e72c254

res_o <= mul.prod(31 downto 0);

[mahdi259]

Thanks for guiding me to trace clock cycles. May your success be inevitable.