[vivado_ip] fix error when AXI port is unconnected (#976)

stnolting · Aug 4, 2024 · e72c254 · e72c254
2 parents 14ef539 + 0402007
commit e72c254
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Showing 5 changed files with 182 additions and 170 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 04.08.2024 | 1.10.2.2 | :bug: fix bug in Vivado IP module (error if AXI port is unconnected) | [#976](https://github.com/stnolting/neorv32/pull/976) |
 | 02.08.2024 | 1.10.2.1 | :warning: rework CFU; remove support for R5-type instructions | [#971](https://github.com/stnolting/neorv32/pull/971) |
 | 29.07.2024 | [**:rocket:1.10.2**](https://github.com/stnolting/neorv32/releases/tag/v1.10.2) | **New release** | |
 | 28.07.2024 | 1.10.1.9 | make SYSINFO.CLK read/**write** | [#966](https://github.com/stnolting/neorv32/pull/966) |

diff --git a/docs/userguide/packaging_vivado.adoc b/docs/userguide/packaging_vivado.adoc
@@ -43,7 +43,6 @@ Vivado project.
 . Click "Select" and close the Settings menu with "Apply" and "OK".
 . You will find the NEORV32 in the "User Repository" section of the Vivado IP catalog.
 
-
 .Combinatorial Loops DRC Errors
 [WARNING]
 If the TRNG is enabled it is recommended to add the following commands to the project's constraints file in order
@@ -55,3 +54,9 @@ set_property SEVERITY {warning} [get_drc_checks LUTLP-1]
 set_property IS_ENABLED FALSE [get_drc_checks LUTLP-1]
 set_property ALLOW_COMBINATORIAL_LOOPS TRUE
 ----
+
+.VHDL2008
+[IMPORTANT]
+If the processor's AXI/IP wrapper (`rtl/system_integration/neorv32_vivado_ip.vhd`) is used in stand-alone mode
+(i.e. not packaged by the default packaging TCL script), make sure to compile this design unit using
+VHDL2008 standard to allow connecting `std_logic_vector` and `std_ulogic_vector` without casting (#974).
diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd
@@ -29,7 +29,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100201"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100202"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width
 

diff --git a/rtl/system_integration/neorv32_vivado_ip.tcl b/rtl/system_integration/neorv32_vivado_ip.tcl
@@ -53,6 +53,9 @@ set_property library neorv32 [get_files [glob $neorv32_home/rtl/core/*.vhd]]
 set_property library neorv32 [get_files [glob $neorv32_home/rtl/core/mem/neorv32_*mem.default.vhd]]
 set_property library neorv32 [get_files [glob $neorv32_home/rtl/system_integration/$rtl_top]]
 
+# Compile top module with VHDL2008 standard to allow connecting std_logic_vector and std_ulogic_vector without casting (#974)
+set_property file_type {VHDL 2008} [get_files [glob $neorv32_home/rtl/system_integration/$rtl_top]]
+
 ##set_property top $rtl_top [current_fileset]
 update_compile_order -fileset sources_1