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[rtl] cleanup memory modules (IMEM & DMEM)
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@stnolting
stnolting committed Nov 1, 2024
1 parent b3155be commit c8ae94c
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38 changes: 19 additions & 19 deletions rtl/core/neorv32_dmem.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@ use neorv32.neorv32_package.all;

entity neorv32_dmem is
generic (
DMEM_SIZE : natural -- processor-internal instruction memory size in bytes, has to be a power of 2
DMEM_SIZE : natural -- memory size in bytes, has to be a power of 2, min 4
);
port (
clk_i : in std_ulogic; -- global clock line
Expand All @@ -38,7 +38,7 @@ architecture neorv32_dmem_rtl of neorv32_dmem is
-- local signals --
signal rdata : std_ulogic_vector(31 downto 0);
signal rden : std_ulogic;
signal addr, addr_ff : std_ulogic_vector(index_size_f(DMEM_SIZE/4)-1 downto 0);
signal addr, addr_ff : unsigned(index_size_f(DMEM_SIZE/4)-1 downto 0);

-- [NOTE] The memory (RAM) is built from 4 individual byte-wide memories as some synthesis tools
-- have issues inferring 32-bit memories with individual byte-enable signals.
Expand All @@ -57,22 +57,22 @@ begin
if rising_edge(clk_i) then
if (bus_req_i.stb = '1') and (bus_req_i.rw = '1') then
if (bus_req_i.ben(0) = '1') then -- byte 0
mem_ram_b0(to_integer(unsigned(addr))) <= bus_req_i.data(7 downto 0);
mem_ram_b0(to_integer(addr)) <= bus_req_i.data(7 downto 0);
end if;
if (bus_req_i.ben(1) = '1') then -- byte 1
mem_ram_b1(to_integer(unsigned(addr))) <= bus_req_i.data(15 downto 8);
mem_ram_b1(to_integer(addr)) <= bus_req_i.data(15 downto 8);
end if;
if (bus_req_i.ben(2) = '1') then -- byte 2
mem_ram_b2(to_integer(unsigned(addr))) <= bus_req_i.data(23 downto 16);
mem_ram_b2(to_integer(addr)) <= bus_req_i.data(23 downto 16);
end if;
if (bus_req_i.ben(3) = '1') then -- byte 3
mem_ram_b3(to_integer(unsigned(addr))) <= bus_req_i.data(31 downto 24);
mem_ram_b3(to_integer(addr)) <= bus_req_i.data(31 downto 24);
end if;
end if;
rdata(7 downto 0) <= mem_ram_b0(to_integer(unsigned(addr)));
rdata(15 downto 8) <= mem_ram_b1(to_integer(unsigned(addr)));
rdata(23 downto 16) <= mem_ram_b2(to_integer(unsigned(addr)));
rdata(31 downto 24) <= mem_ram_b3(to_integer(unsigned(addr)));
rdata(7 downto 0) <= mem_ram_b0(to_integer(addr));
rdata(15 downto 8) <= mem_ram_b1(to_integer(addr));
rdata(23 downto 16) <= mem_ram_b2(to_integer(addr));
rdata(31 downto 24) <= mem_ram_b3(to_integer(addr));
end if;
end process mem_access;
addr_ff <= (others => '0'); -- unused
Expand All @@ -86,28 +86,28 @@ begin
addr_ff <= addr;
if (bus_req_i.stb = '1') and (bus_req_i.rw = '1') then
if (bus_req_i.ben(0) = '1') then -- byte 0
mem_ram_b0(to_integer(unsigned(addr))) <= bus_req_i.data(7 downto 0);
mem_ram_b0(to_integer(addr)) <= bus_req_i.data(7 downto 0);
end if;
if (bus_req_i.ben(1) = '1') then -- byte 1
mem_ram_b1(to_integer(unsigned(addr))) <= bus_req_i.data(15 downto 8);
mem_ram_b1(to_integer(addr)) <= bus_req_i.data(15 downto 8);
end if;
if (bus_req_i.ben(2) = '1') then -- byte 2
mem_ram_b2(to_integer(unsigned(addr))) <= bus_req_i.data(23 downto 16);
mem_ram_b2(to_integer(addr)) <= bus_req_i.data(23 downto 16);
end if;
if (bus_req_i.ben(3) = '1') then -- byte 3
mem_ram_b3(to_integer(unsigned(addr))) <= bus_req_i.data(31 downto 24);
mem_ram_b3(to_integer(addr)) <= bus_req_i.data(31 downto 24);
end if;
end if;
end if;
end process mem_access;
rdata(7 downto 0) <= mem_ram_b0(to_integer(unsigned(addr_ff)));
rdata(15 downto 8) <= mem_ram_b1(to_integer(unsigned(addr_ff)));
rdata(23 downto 16) <= mem_ram_b2(to_integer(unsigned(addr_ff)));
rdata(31 downto 24) <= mem_ram_b3(to_integer(unsigned(addr_ff)));
rdata(7 downto 0) <= mem_ram_b0(to_integer(addr_ff));
rdata(15 downto 8) <= mem_ram_b1(to_integer(addr_ff));
rdata(23 downto 16) <= mem_ram_b2(to_integer(addr_ff));
rdata(31 downto 24) <= mem_ram_b3(to_integer(addr_ff));
end generate;

-- word aligned access address --
addr <= bus_req_i.addr(index_size_f(DMEM_SIZE/4)+1 downto 2);
addr <= unsigned(bus_req_i.addr(index_size_f(DMEM_SIZE/4)+1 downto 2));


-- Bus Response ---------------------------------------------------------------------------
Expand Down
64 changes: 31 additions & 33 deletions rtl/core/neorv32_imem.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,8 +21,8 @@ use neorv32.neorv32_application_image.all; -- generated by the image generator

entity neorv32_imem is
generic (
IMEM_SIZE : natural; -- processor-internal instruction memory size in bytes, has to be a power of 2
IMEM_AS_IROM : boolean -- implement IMEM as pre-initialized read-only memory?
IMEM_SIZE : natural; -- memory size in bytes, has to be a power of 2, min 4
IMEM_INIT : boolean -- implement IMEM as pre-initialized read-only memory?
);
port (
clk_i : in std_ulogic; -- global clock line
Expand All @@ -37,16 +37,14 @@ architecture neorv32_imem_rtl of neorv32_imem is
-- alternative memory description style --
constant alt_style_c : boolean := false; -- [TIP] enable this if synthesis fails to infer block RAM

-- ROM - initialized with executable code --
constant imem_app_size_c : natural := (application_init_image'length)*4; -- application (image) size in bytes
constant mem_rom_c : mem32_t(0 to IMEM_SIZE/4-1) := mem32_init_f(application_init_image, IMEM_SIZE/4);

-- local signals --
signal rdata : std_ulogic_vector(31 downto 0);
signal rden : std_ulogic;
signal addr, addr_ff : std_ulogic_vector(index_size_f(IMEM_SIZE/4)-1 downto 0);

-- application (image) size in bytes --
constant imem_app_size_c : natural := (application_init_image'length)*4;

-- ROM - initialized with executable code --
constant mem_rom_c : mem32_t(0 to IMEM_SIZE/4-1) := mem32_init_f(application_init_image, IMEM_SIZE/4);
signal addr, addr_ff : unsigned(index_size_f(IMEM_SIZE/4)-1 downto 0);

-- [NOTE] The memory (RAM) is built from 4 individual byte-wide memories as some synthesis tools
-- have issues inferring 32-bit memories with individual byte-enable signals.
Expand All @@ -60,9 +58,9 @@ begin
-- -------------------------------------------------------------------------------------------
assert false report
"[NEORV32] Implementing processor-internal IMEM as " &
cond_sel_string_f(IMEM_AS_IROM, "pre-initialized ROM.", "blank RAM.") severity note;
cond_sel_string_f(IMEM_INIT, "pre-initialized ROM.", "blank RAM.") severity note;

assert not ((IMEM_AS_IROM = true) and (imem_app_size_c > IMEM_SIZE)) report
assert not ((IMEM_INIT = true) and (imem_app_size_c > IMEM_SIZE)) report
"[NEORV32] Application image (" & natural'image(imem_app_size_c) &
" bytes) does not fit into processor-internal IMEM (" &
natural'image(IMEM_SIZE) & " bytes)!" severity error;
Expand All @@ -71,14 +69,14 @@ begin
-- Implement IMEM as pre-initialized ROM --------------------------------------------------
-- -------------------------------------------------------------------------------------------
imem_rom:
if IMEM_AS_IROM generate
if IMEM_INIT generate

imem_rom_default: -- default memory HDL style
if not alt_style_c generate
mem_access: process(clk_i)
begin
if rising_edge(clk_i) then
rdata <= mem_rom_c(to_integer(unsigned(addr)));
rdata <= mem_rom_c(to_integer(addr));
end if;
end process mem_access;
addr_ff <= (others => '0'); -- unused
Expand All @@ -92,19 +90,19 @@ begin
addr_ff <= addr;
end if;
end process mem_access;
rdata <= mem_rom_c(to_integer(unsigned(addr_ff)));
rdata <= mem_rom_c(to_integer(addr_ff));
end generate;

end generate;

-- word aligned access address --
addr <= bus_req_i.addr(index_size_f(IMEM_SIZE/4)+1 downto 2);
addr <= unsigned(bus_req_i.addr(index_size_f(IMEM_SIZE/4)+1 downto 2));


-- Implement IMEM as non-initialized RAM --------------------------------------------------
-- -------------------------------------------------------------------------------------------
imem_ram:
if not IMEM_AS_IROM generate
if not IMEM_INIT generate

imem_ram_default: -- default memory HDL style
if not alt_style_c generate
Expand All @@ -113,22 +111,22 @@ begin
if rising_edge(clk_i) then
if (bus_req_i.stb = '1') and (bus_req_i.rw = '1') then
if (bus_req_i.ben(0) = '1') then -- byte 0
mem_ram_b0(to_integer(unsigned(addr))) <= bus_req_i.data(7 downto 0);
mem_ram_b0(to_integer(addr)) <= bus_req_i.data(7 downto 0);
end if;
if (bus_req_i.ben(1) = '1') then -- byte 1
mem_ram_b1(to_integer(unsigned(addr))) <= bus_req_i.data(15 downto 8);
mem_ram_b1(to_integer(addr)) <= bus_req_i.data(15 downto 8);
end if;
if (bus_req_i.ben(2) = '1') then -- byte 2
mem_ram_b2(to_integer(unsigned(addr))) <= bus_req_i.data(23 downto 16);
mem_ram_b2(to_integer(addr)) <= bus_req_i.data(23 downto 16);
end if;
if (bus_req_i.ben(3) = '1') then -- byte 3
mem_ram_b3(to_integer(unsigned(addr))) <= bus_req_i.data(31 downto 24);
mem_ram_b3(to_integer(addr)) <= bus_req_i.data(31 downto 24);
end if;
end if;
rdata(7 downto 0) <= mem_ram_b0(to_integer(unsigned(addr)));
rdata(15 downto 8) <= mem_ram_b1(to_integer(unsigned(addr)));
rdata(23 downto 16) <= mem_ram_b2(to_integer(unsigned(addr)));
rdata(31 downto 24) <= mem_ram_b3(to_integer(unsigned(addr)));
rdata(7 downto 0) <= mem_ram_b0(to_integer(addr));
rdata(15 downto 8) <= mem_ram_b1(to_integer(addr));
rdata(23 downto 16) <= mem_ram_b2(to_integer(addr));
rdata(31 downto 24) <= mem_ram_b3(to_integer(addr));
end if;
end process mem_access;
addr_ff <= (others => '0'); -- unused
Expand All @@ -142,24 +140,24 @@ begin
addr_ff <= addr;
if (bus_req_i.stb = '1') and (bus_req_i.rw = '1') then
if (bus_req_i.ben(0) = '1') then -- byte 0
mem_ram_b0(to_integer(unsigned(addr))) <= bus_req_i.data(7 downto 0);
mem_ram_b0(to_integer(addr)) <= bus_req_i.data(7 downto 0);
end if;
if (bus_req_i.ben(1) = '1') then -- byte 1
mem_ram_b1(to_integer(unsigned(addr))) <= bus_req_i.data(15 downto 8);
mem_ram_b1(to_integer(addr)) <= bus_req_i.data(15 downto 8);
end if;
if (bus_req_i.ben(2) = '1') then -- byte 2
mem_ram_b2(to_integer(unsigned(addr))) <= bus_req_i.data(23 downto 16);
mem_ram_b2(to_integer(addr)) <= bus_req_i.data(23 downto 16);
end if;
if (bus_req_i.ben(3) = '1') then -- byte 3
mem_ram_b3(to_integer(unsigned(addr))) <= bus_req_i.data(31 downto 24);
mem_ram_b3(to_integer(addr)) <= bus_req_i.data(31 downto 24);
end if;
end if;
end if;
end process mem_access;
rdata(7 downto 0) <= mem_ram_b0(to_integer(unsigned(addr_ff)));
rdata(15 downto 8) <= mem_ram_b1(to_integer(unsigned(addr_ff)));
rdata(23 downto 16) <= mem_ram_b2(to_integer(unsigned(addr_ff)));
rdata(31 downto 24) <= mem_ram_b3(to_integer(unsigned(addr_ff)));
rdata(7 downto 0) <= mem_ram_b0(to_integer(addr_ff));
rdata(15 downto 8) <= mem_ram_b1(to_integer(addr_ff));
rdata(23 downto 16) <= mem_ram_b2(to_integer(addr_ff));
rdata(31 downto 24) <= mem_ram_b3(to_integer(addr_ff));
end generate;

end generate;
Expand All @@ -174,7 +172,7 @@ begin
bus_rsp_o.ack <= '0';
elsif rising_edge(clk_i) then
rden <= bus_req_i.stb and (not bus_req_i.rw);
if (IMEM_AS_IROM = true) then
if (IMEM_INIT = true) then
bus_rsp_o.ack <= bus_req_i.stb and (not bus_req_i.rw); -- read-only!
else
bus_rsp_o.ack <= bus_req_i.stb;
Expand Down

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