🧪 convert VHDL memory images into full-scale VHDL packages #2807

	name: Processor

	on:
	push:
	paths:
	- 'rtl/**'
	- 'sw/**'
	- 'sim/**'
	- '.github/workflows/Processor.yml'
	pull_request:
	paths:
	- 'rtl/**'
	- 'sw/**'
	- 'sim/**'
	- '.github/workflows/Processor.yml'
	workflow_dispatch:

	jobs:

	sim_default_tb:
	runs-on: ubuntu-latest
	name: 'processor simulation'
	strategy:
	fail-fast: false
	matrix:
	example:
	- processor_check
	- hello_world

	steps:

	- name: '🧰 Repository Checkout'
	uses: actions/checkout@v4

	- name: '📦 Install RISC-V GCC'
	run: \|
	wget -q https://github.com/stnolting/riscv-gcc-prebuilt/releases/download/rv32i-131023/riscv32-unknown-elf.gcc-13.2.0.tar.gz
	mkdir $GITHUB_WORKSPACE/riscv-gcc
	tar -xzf riscv32-unknown-elf.gcc-13.2.0.tar.gz -C $GITHUB_WORKSPACE/riscv-gcc
	echo $GITHUB_WORKSPACE/riscv-gcc/bin >> $GITHUB_PATH

	- name: '📦 Install GHDL'
	uses: ghdl/setup-ghdl-ci@nightly

	- name: '🔍 Check tools'
	run: \|
	riscv32-unknown-elf-gcc -v
	ghdl -v

	- name: '⚙️ Build Software Framework Tests'
	run: \|
	make -C sw/example/processor_check check
	make -C sw/example clean_all exe
	make -C sw/bootloader clean_all info bootloader

	- name: '🚧 Compile executable and run simulation'
	run: \|
	make -C sw/example/${{ matrix.example }} \
	USER_FLAGS+="-DUART0_SIM_MODE -DUART1_SIM_MODE" \
	clean_all \
	info \
	all \
	sim-check

Provide feedback