🧪 convert VHDL memory images into full-scale VHDL packages #2800

	name: Processor

	on:
	push:
	paths:
	- 'rtl/**'
	- 'sw/**'
	- 'sim/**'
	- '.github/workflows/Processor.yml'
	pull_request:
	paths:
	- 'rtl/**'
	- 'sw/**'
	- 'sim/**'
	- '.github/workflows/Processor.yml'
	workflow_dispatch:

	jobs:

	Software:
	runs-on: ubuntu-latest
	container: ghcr.io/stnolting/neorv32/sim

	steps:

	- name: '🧰 Repository Checkout'
	uses: actions/checkout@v4

	- name: '⚙️ Build Software Framework Tests'
	run: \|
	make -C sw/example/processor_check check
	make -C sw/example clean_all exe
	make -C sw/bootloader clean_all info bootloader

	Default_TB:
	runs-on: ubuntu-latest
	name: 'Default testbench'
	strategy:
	fail-fast: false
	matrix:
	example:
	- processor_check
	- hello_world

	steps:

	- name: '🧰 Repository Checkout'
	uses: actions/checkout@v4

	- name: '🚧 Build and install software; then simulate with shell script'
	uses: docker://ghcr.io/stnolting/neorv32/sim
	# Redirect UART0 TX to text.io simulation output via <UARTx_SIM_MODE> user flags
	with:
	args: >-
	make -C sw/example/${{ matrix.example }}
	clean_all
	USER_FLAGS+="-DUART0_SIM_MODE -DUART1_SIM_MODE -flto"
	EFFORT=-Os
	MARCH=rv32ima_zicsr_zifencei
	info
	all
	sim-check

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