A 5 stage pipeline that handles RV32I instructions.
Current Status: 5 stage pipeline is implemented.
Testbench is in progress. The following instructions have been loosely verified to work:
Repition of ADDI Instruction.
Datapath Pipeline
ADDI Waveform
Right Now IMEM is a 4Kb Instruction Cache. No method of fetching from main memory or dynamic cache transfer
To be added later
Risc V RV32I Instruction Format
Instruction Variants
Type R, I, S, B, U, J
(Image from RV32I Specification Section 2.3: https://riscv.org/wp-content/uploads/2019/06/riscv-spec.pdf)
Immediate Construction Format
Important to the Immediate Generator located in immGen/immGen.v
Control Unit
pc_sel Signal
Current Status
11/6/23 : Currently adding instructions into control unit
Control Signals
BrEq : 1
BrLT : 2
a_sel ...
b_sel ...
alu_sel ...
mem_wr ...
RegWEn ...
immSel ...
BrUn : 9
pc_sel : A
wb_sel : B
Ctl 1 2 3 4 5 6 7 8 9 A B
LUI x x 0 1 9 0 1 4 x 0 1
AUIPC x x 1 1 2 0 1 4 x 0 1
JAL x x 1 1 2 0 1 5 x 1 2
JALR x x 0 1 2 0 1 1 x 1 2
BEQ 0 x 0 0 2 0 0 3 x 0 x
BEQ 1 x 0 0 2 0 0 3 x 1 x
BNE 1 x 0 0 2 0 0 3 x 0 x
BNE 0 x 0 0 2 0 0 3 x 1 x
BLT x 0 0 0 2 0 0 3 0 0 x
BLT x 1 0 0 2 0 0 3 0 1 x
BGE x 0 0 0 2 0 0 3 0 1 x
BGE x 1 0 0 2 0 0 3 0 0 x
BLT x 0 0 0 2 0 0 3 1 0 x
BLT x 1 0 0 2 0 0 3 1 1 x
BGE x 0 0 0 2 0 0 3 1 1 x
BGE x 1 0 0 2 0 0 3 1 0 x
LB x x 0 1 2 0 1 1 0 0 0
LH x x 0 1 2 0 1 1 0 0 0
LW x x 0 1 2 0 1 1 0 0 0
LBU x x 0 1 2 0 1 1 0 0 0
LHU x x 0 1 2 0 1 1 0 0 0
SB x x 0 1 2 1 0 2 0 0 0
SH x x 0 1 2 1 0 2 0 0 0
SW x x 0 1 2 1 0 2 0 0 0
ADDI x x 0 1 2 0 1 1 0 0 1
STLI x x 0 1 8 0 1 1 0 0 1
FPGA Tests: Assembly Programs: https://marz.utk.edu/my-courses/cosc230/book/example-risc-v-assembly-programs/ Assembler: https://www.riscvassembler.org/