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shibatch · Dec 18, 2023 · 4051f42 · 4051f42
1 parent 018f5f8
commit 4051f42
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Showing 3 changed files with 73 additions and 0 deletions.
diff --git a/src/arch/helperrvv.h b/src/arch/helperrvv.h
@@ -16,22 +16,27 @@
 #elif CONFIG == 7
 // 128-bit vector length
 #define ISANAME "RISC-V Vector Extension 128-bit"
+#define LOG2VECTLENDP 1
 #define SLEEF_RVV_VLEN ((1 << 7) / 8)
 #elif CONFIG == 8
 // 256-bit vector length
 #define ISANAME "RISC-V Vector Extension 256-bit"
+#define LOG2VECTLENDP 2
 #define SLEEF_RVV_VLEN ((1 << 8) / 8)
 #elif CONFIG == 9
 // 512-bit vector length
 #define ISANAME "RISC-V Vector Extension 512-bit"
+#define LOG2VECTLENDP 3
 #define SLEEF_RVV_VLEN ((1 << 9) / 8)
 #elif CONFIG == 10
 // 1024-bit vector length
 #define ISANAME "RISC-V Vector Extension 1024-bit"
+#define LOG2VECTLENDP 4
 #define SLEEF_RVV_VLEN ((1 << 10) / 8)
 #elif CONFIG == 11
 // 2048-bit vector length
 #define ISANAME "RISC-V Vector Extension 2048-bit"
+#define LOG2VECTLENDP 5
 #define SLEEF_RVV_VLEN ((1 << 11) / 8)
 #else
 #error CONFIG macro invalid or not defined
@@ -278,6 +283,8 @@ typedef vint32m8_t dfi_t;
 #error "unknown rvv lmul"
 #endif // ENABLE_RVVM1
 
+typedef vquad vargquad;
+
 ////////////////////////////////////////////////////////////////////////////////
 // Single-Precision Functions
 ////////////////////////////////////////////////////////////////////////////////
@@ -1064,4 +1071,12 @@ static INLINE vint vand_vi_vo_vi(vopmask x, vint y) {
 }
 #endif // ENABLE_RVV_DP
 
+/****************************************/
+/* DFT Operations                       */
+/****************************************/
+
+static INLINE vdouble vposneg_vd_vd(vdouble d) {
+  // not implemented
+}
+
 #endif // HELPERRVV_H
diff --git a/src/dft/CMakeLists.txt b/src/dft/CMakeLists.txt
@@ -75,6 +75,46 @@ set(MACRODEF_sve2048dp BASETYPEID=1 ENABLE_SVE CONFIG=11)
 set(CFLAGS_sve2048dp ${FLAGS_ENABLE_SVE})
 set(MACRODEF_sve2048sp BASETYPEID=2 ENABLE_SVE CONFIG=11)
 set(CFLAGS_sve2048sp ${FLAGS_ENABLE_SVE})
+set(MACRODEF_rvvm1128sp BASETYPEID=1 ENABLE_RVVM1 CONFIG=7)
+set(CFLAGS_rvvm1128sp ${FLAGS_ENABLE_RVVM1})
+set(MACRODEF_rvvm1128sp BASETYPEID=2 ENABLE_RVVM1 CONFIG=7)
+set(CFLAGS_rvvm1128sp ${FLAGS_ENABLE_RVVM1})
+set(MACRODEF_rvvm1256dp BASETYPEID=1 ENABLE_RVVM1 CONFIG=8)
+set(CFLAGS_rvvm1256dp ${FLAGS_ENABLE_RVVM1})
+set(MACRODEF_rvvm1256sp BASETYPEID=2 ENABLE_RVVM1 CONFIG=8)
+set(CFLAGS_rvvm1256sp ${FLAGS_ENABLE_RVVM1})
+set(MACRODEF_rvvm1512dp BASETYPEID=1 ENABLE_RVVM1 CONFIG=9)
+set(CFLAGS_rvvm1512dp ${FLAGS_ENABLE_RVVM1})
+set(MACRODEF_rvvm1512sp BASETYPEID=2 ENABLE_RVVM1 CONFIG=9)
+set(CFLAGS_rvvm1512sp ${FLAGS_ENABLE_RVVM1})
+set(MACRODEF_rvvm11024dp BASETYPEID=1 ENABLE_RVVM1 CONFIG=10)
+set(CFLAGS_rvvm11024dp ${FLAGS_ENABLE_RVVM1})
+set(MACRODEF_rvvm11024sp BASETYPEID=2 ENABLE_RVVM1 CONFIG=10)
+set(CFLAGS_rvvm11024sp ${FLAGS_ENABLE_RVVM1})
+set(MACRODEF_rvvm12048dp BASETYPEID=1 ENABLE_RVVM1 CONFIG=11)
+set(CFLAGS_rvvm12048dp ${FLAGS_ENABLE_RVVM1})
+set(MACRODEF_rvvm12048sp BASETYPEID=2 ENABLE_RVVM1 CONFIG=11)
+set(CFLAGS_rvvm12048sp ${FLAGS_ENABLE_RVVM1})
+set(MACRODEF_rvvm2128dp BASETYPEID=1 ENABLE_RVVM2 CONFIG=7)
+set(CFLAGS_rvvm2128dp ${FLAGS_ENABLE_RVVM2})
+set(MACRODEF_rvvm2128sp BASETYPEID=2 ENABLE_RVVM2 CONFIG=7)
+set(CFLAGS_rvvm2128sp ${FLAGS_ENABLE_RVVM2})
+set(MACRODEF_rvvm2256dp BASETYPEID=1 ENABLE_RVVM2 CONFIG=8)
+set(CFLAGS_rvvm2256dp ${FLAGS_ENABLE_RVVM2})
+set(MACRODEF_rvvm2256sp BASETYPEID=2 ENABLE_RVVM2 CONFIG=8)
+set(CFLAGS_rvvm2256sp ${FLAGS_ENABLE_RVVM2})
+set(MACRODEF_rvvm2512dp BASETYPEID=1 ENABLE_RVVM2 CONFIG=9)
+set(CFLAGS_rvvm2512dp ${FLAGS_ENABLE_RVVM2})
+set(MACRODEF_rvvm2512sp BASETYPEID=2 ENABLE_RVVM2 CONFIG=9)
+set(CFLAGS_rvvm2512sp ${FLAGS_ENABLE_RVVM2})
+set(MACRODEF_rvvm21024dp BASETYPEID=1 ENABLE_RVVM2 CONFIG=10)
+set(CFLAGS_rvvm21024dp ${FLAGS_ENABLE_RVVM2})
+set(MACRODEF_rvvm21024sp BASETYPEID=2 ENABLE_RVVM2 CONFIG=10)
+set(CFLAGS_rvvm21024sp ${FLAGS_ENABLE_RVVM2})
+set(MACRODEF_rvvm22048dp BASETYPEID=1 ENABLE_RVVM2 CONFIG=11)
+set(CFLAGS_rvvm22048dp ${FLAGS_ENABLE_RVVM2})
+set(MACRODEF_rvvm22048sp BASETYPEID=2 ENABLE_RVVM2 CONFIG=11)
+set(CFLAGS_rvvm22048sp ${FLAGS_ENABLE_RVVM2})
 set(MACRODEF_vsxdp BASETYPEID=1 ENABLE_VSX CONFIG=1)
 set(CFLAGS_vsxdp ${FLAGS_ENABLE_VSX})
 set(MACRODEF_vsxsp BASETYPEID=2 ENABLE_VSX CONFIG=1)
@@ -139,6 +179,16 @@ if (COMPILER_SUPPORTS_NEON32)
   set(ISALIST_SP ${ISALIST_SP} neon32sp)
 endif(COMPILER_SUPPORTS_NEON32)
 
+if (COMPILER_SUPPORTS_RVVM1)
+  set(ISALIST_SP ${ISALIST_SP} rvvm1128sp rvvm1256sp rvvm1512sp rvvm11024sp rvvm12048sp)
+  set(ISALIST_DP ${ISALIST_DP} rvvm1128dp rvvm1256dp rvvm1512dp rvvm11024dp rvvm12048dp)
+endif(COMPILER_SUPPORTS_RVVM1)
+
+if (COMPILER_SUPPORTS_RVVM2)
+  set(ISALIST_SP ${ISALIST_SP} rvvm2128sp rvvm2256sp rvvm2512sp rvvm21024sp rvvm22048sp)
+  set(ISALIST_DP ${ISALIST_DP} rvvm2128dp rvvm2256dp rvvm2512dp rvvm21024dp rvvm22048dp)
+endif(COMPILER_SUPPORTS_RVVM2)
+
 if (COMPILER_SUPPORTS_VSX)
   set(ISALIST_SP ${ISALIST_SP} vsxsp)
   set(ISALIST_DP ${ISALIST_DP} vsxdp)

diff --git a/src/dft/vectortype.h b/src/dft/vectortype.h
@@ -37,6 +37,14 @@
 #include "helpersve.h"
 #endif
 
+#ifdef ENABLE_RVVM1
+#include "helperrvv.h"
+#endif
+
+#ifdef ENABLE_RVVM2
+#include "helperrvv.h"
+#endif
+
 #ifdef ENABLE_VSX
 #include "helperpower_128.h"
 #endif