update to issue_18.rdl example

sdnellen · Jan 9, 2020 · 15a9790 · 15a9790
1 parent d3f7a02
commit 15a9790
Show file tree

Hide file tree

Showing 2 changed files with 20 additions and 1 deletion.
diff --git a/rdl_examples/issue_18.rdl b/rdl_examples/issue_18.rdl
@@ -35,8 +35,27 @@ regfile other_regs_defns_rf {
 	attr_resetsignal_t attr_rstsignal;  // SDN - missing semi
 };
 
+
+field fld_4b_t {
+	hw = r; sw = rw; fieldwidth = 4; reset = 0;
+};
+reg attr_reg_t {
+    default resetsignal = test_rst_sig;  // set a default reset to be used for all fields in this reg
+    fld_4b_t fld1;
+    fld_4b_t fld2;
+    fld_4b_t fld3;
+};
+
 addrmap ordtreg_regs {
 	test_rst_sig test_rst_sig;
 	other_regs_defns_rf other_rf @ 0x000100;
 	other_rf.attr_rstsignal.extsig_rst_field1->resetsignal = test_rst_sig;
+
+	attr_reg_t another_reg @ 0x200;
+	//another_reg.fld1->resetsignal = test_rst_sig;
+	//another_reg.fld2->resetsignal = test_rst_sig;
+	//another_reg.fld3->resetsignal = test_rst_sig;
+	//another_reg.*->resetsignal = test_rst_sig;
+
+
 } basemap;  // SDN - instanced addrmap
diff --git a/src/ordt/extract/Ordt.java b/src/ordt/extract/Ordt.java
@@ -36,7 +36,7 @@
 
 public class Ordt {
 
-	private static String version = "191222.01";
+	private static String version = "200108.01";
 	private static DebugController debug = new MyDebugController(); // override design annotations, input/output files
 
 	public enum InputType { RDL, JSPEC };