hal: code cleanup on derived traits

Signed-off-by: Zhouqi Jiang <[email protected]>

src/ccu.rs

@@ -48,7 +48,7 @@ pub struct RegisterBlock {
 }
 
 /// CPU PLL Control register.
-#[derive(Clone, Copy)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct PllCpuControl(u32);
 
@@ -148,7 +148,7 @@ impl PllCpuControl {
 }
 
 /// DDR PLL Control register.
-#[derive(Clone, Copy)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct PllDdrControl(u32);
 
@@ -259,7 +259,7 @@ impl PllDdrControl {
 }
 
 /// Peripheral PLL Control register 0.
-#[derive(Clone, Copy)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct PllPeri0Control(u32);
 
@@ -381,7 +381,7 @@ impl PllPeri0Control {
 }
 
 /// AXI CPU clock source.
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 pub enum CpuClockSource {
     /// 24-MHz external oscillator.
     Osc24M,
@@ -400,7 +400,7 @@ pub enum CpuClockSource {
 }
 
 /// CPU AXI Configuration register.
-#[derive(Clone, Copy)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct CpuAxiConfig(u32);
 
@@ -481,7 +481,7 @@ impl CpuAxiConfig {
 }
 
 /// MBUS Clock register.
-#[derive(Clone, Copy)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct MbusClock(u32);
 
@@ -506,7 +506,7 @@ impl MbusClock {
 }
 
 /// DRAM Clock Register.
-#[derive(Clone, Copy)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct DramClock(u32);
 
@@ -589,7 +589,7 @@ impl DramClock {
 }
 
 /// Dram Bus Gating Reset register.
-#[derive(Clone, Copy)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct DramBusGating(u32);
 
@@ -620,7 +620,7 @@ impl DramBusGating {
 }
 
 /// Clock divide factor N.
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 pub enum FactorN {
     /// Don't divide.
     N1,
@@ -633,7 +633,7 @@ pub enum FactorN {
 }
 
 /// Clock divide factor P.
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 pub enum FactorP {
     /// Don't divide.
     P1,
@@ -644,9 +644,10 @@ pub enum FactorP {
 }
 
 /// UART Bus Gating Reset register.
-#[derive(Clone, Copy)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct UartBusGating(u32);
+
 impl UartBusGating {
     /// Disable clock gate for UART `I`.
     #[inline]
@@ -671,7 +672,7 @@ impl UartBusGating {
 }
 
 /// SPI Clock Register.
-#[derive(Clone, Copy)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct SpiClock(u32);
 
@@ -738,7 +739,7 @@ impl SpiClock {
 }
 
 /// SPI clock source.
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 pub enum SpiClockSource {
     /// HOSC.
     Hosc,
@@ -753,7 +754,7 @@ pub enum SpiClockSource {
 }
 
 /// SPI Bus Gating Reset register.
-#[derive(Clone, Copy)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct SpiBusGating(u32);
 
@@ -806,6 +807,7 @@ pub trait ClockConfig {
 /// Universal Asynchronous Receiver-Transmitter clock gate.
 ///
 /// UART peripheral should be indexed by type parameter `IDX`.
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 pub struct UART<const IDX: usize>;
 
 impl<const I: usize> ClockGate for UART<I> {
@@ -828,6 +830,7 @@ impl<const I: usize> ClockGate for UART<I> {
 }
 
 /// Serial Peripheral Interface clock gate.
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 pub struct SPI<const IDX: usize>;
 
 impl<const I: usize> ClockGate for SPI<I> {

src/gpio.rs

@@ -54,6 +54,7 @@ pub struct PioPow {
 }
 
 /// External interrupt event.
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 pub enum Event {
     PositiveEdge,
     NegativeEdge,

src/smhc.rs

@@ -56,12 +56,12 @@ pub struct RegisterBlock {
 }
 
 /// Global control register.
-#[derive(Clone, Copy, Debug, PartialEq, Eq, Default)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct GlobalControl(u32);
 
 /// FIFO access mode.
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 pub enum AccessMode {
     // Dma bus.
     Dma,
@@ -70,7 +70,7 @@ pub enum AccessMode {
 }
 
 /// DDR mode.
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 pub enum DdrMode {
     // SDR mode.
     Sdr,
@@ -175,7 +175,7 @@ impl GlobalControl {
 }
 
 /// Clock control register.
-#[derive(Clone, Copy, Debug, PartialEq, Eq, Default)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct ClockControl(u32);
 
@@ -245,12 +245,12 @@ impl TimeOut {
 }
 
 /// Bus width register.
-#[derive(Clone, Copy, Debug, PartialEq, Eq, Default)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct BusWidth(u32);
 
 /// Bus width bits.
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 pub enum BusWidthBits {
     /// 1 bit.
     OneBit,
@@ -280,7 +280,7 @@ impl BusWidth {
 }
 
 /// Block size register.
-#[derive(Clone, Copy, Debug, PartialEq, Eq, Default)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct BlockSize(u32);
 
@@ -299,7 +299,7 @@ impl BlockSize {
 }
 
 /// Byte count register.
-#[derive(Clone, Copy, Debug, PartialEq, Eq, Default)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct ByteCount(u32);
 
@@ -318,12 +318,12 @@ impl ByteCount {
 }
 
 /// Command register.
-#[derive(Clone, Copy, Debug, PartialEq, Eq, Default)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct Command(u32);
 
 /// Transfer direction.
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 pub enum TransferDirection {
     /// Read from card.
     Read,
@@ -514,7 +514,7 @@ impl Command {
 }
 
 /// Argument register.
-#[derive(Clone, Copy, Debug, PartialEq, Eq, Default)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct Argument(u32);
 
@@ -534,12 +534,12 @@ impl Argument {
 }
 
 /// Interrupt mask register.
-#[derive(Clone, Copy, Debug, PartialEq, Eq, Default)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct InterruptMask(u32);
 
 /// Interrupt type.
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 pub enum Interrupt {
     CardRemoved,
     CardInserted,
@@ -655,7 +655,7 @@ impl InterruptMask {
 }
 
 /// Masked Interrupt state masked register.
-#[derive(Clone, Copy, Debug, PartialEq, Eq, Default)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct InterruptStateMasked(u32);
 
@@ -706,7 +706,7 @@ impl InterruptStateMasked {
 }
 
 /// Raw Interrupt state register.
-#[derive(Clone, Copy, Debug, PartialEq, Eq, Default)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct InterruptStateRaw(u32);
 
@@ -781,7 +781,7 @@ impl InterruptStateRaw {
 }
 
 /// State register.
-#[derive(Clone, Copy, Debug, PartialEq, Eq, Default)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 // note: read-only register, no write functions
 pub struct Status(u32);
@@ -815,12 +815,12 @@ impl Status {
 }
 
 /// FIFO water level register.
-#[derive(Clone, Copy, Debug, PartialEq, Eq, Default)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct FifoWaterLevel(u32);
 
 /// Burst size.
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 pub enum BurstSize {
     /// 1 byte.
     OneBit,
@@ -876,12 +876,12 @@ impl FifoWaterLevel {
 }
 
 /// New timing set register.
-#[derive(Clone, Copy, Debug, PartialEq, Eq, Default)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct NewTimingSet(u32);
 
 /// New timing set timing phase.
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 pub enum NtsTimingPhase {
     Offset90,
     Offset180,
@@ -927,12 +927,12 @@ impl NewTimingSet {
 }
 
 /// Drive Delay Control register.
-#[derive(Clone, Copy)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
 pub struct DriveDelayControl(u32);
 
 /// Drive delay control timing phase.
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 pub enum DdcTimingPhase {
     /// Offset is 90 degrees at SDR mode, 45 degrees at DDR mode.
     Sdr90Ddr45,

src/spi.rs

@@ -239,6 +239,7 @@ impl BurstControl {
 }
 
 /// Transmit data register.
+#[derive(Debug)]
 #[repr(transparent)]
 pub struct TXD(UnsafeCell<u32>);
 
@@ -261,6 +262,7 @@ impl TXD {
 }
 
 /// Receive data register.
+#[derive(Debug)]
 #[repr(transparent)]
 pub struct RXD(UnsafeCell<u32>);
 
@@ -283,6 +285,7 @@ impl RXD {
 }
 
 /// Managed SPI structure with peripheral and pins.
+#[derive(Debug)]
 pub struct Spi<SPI, const I: usize, PINS: Pins<I>> {
     spi: SPI,
     pins: PINS,