Introduce RISC-V architecture support

[TimePrinciple]

Summary of the PR

Introduce RISC-V architecture to loader, bringing #163 forward.

Requirements

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• All commits in this PR have Signed-Off-By trailers (with
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  summary and max 75 characters for each description line.
• All added/changed functionality has a corresponding unit/integration
  test.
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• Any newly added unsafe code is properly documented.

[TimePrinciple]

@roypat @rbradford @ShadowCurse PTAL when convenient :)

[roypat]

I feel like there is a lot of code duplicated between the ARM and RISC implementations that doesn't really need to be duplicated like this. Can you have a look at that, to see where we can reuse instead? :o

[TimePrinciple]

I feel like there is a lot of code duplicated between the ARM and RISC implementations that doesn't really need to be duplicated like this. Can you have a look at that, to see where we can reuse instead? :o

Yes, I noticed that, I just copied these files incase there is something to be diverged in the future

I can try to merge the common part as possible, but what should we name that, like riscs ? :o

[rbradford]

I feel like there is a lot of code duplicated between the ARM and RISC implementations that doesn't really need to be duplicated like this. Can you have a look at that, to see where we can reuse instead? :o

Yes, I noticed that, I just copied these files incase there is something to be diverged in the future

I can try to merge the common part as possible, but what should we name that, like riscs ? :o

Maybe move the fdt code to a higher level and then pub use to expose it from the arch module and keep the same API?

[rbradford]

After the refactoring this change is lovely and compact.